6c05b2479e
Also added a condition (!ARCH_BOARD_CUSTOM) for preventing that out-of-tree ESP32-based custom boards carry out the in-tree common directory.
119 lines
3.3 KiB
Plaintext
119 lines
3.3 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_BOARD_ESP32_DEVKITC
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if PM
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config PM_ALARM_SEC
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int "PM_STANDBY delay (seconds)"
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default 15
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depends on PM
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---help---
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Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
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config PM_ALARM_NSEC
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int "PM_STANDBY delay (nanoseconds)"
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default 0
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depends on PM
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---help---
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Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
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config PM_SLEEP_WAKEUP_SEC
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int "PM_SLEEP delay (seconds)"
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default 20
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depends on PM
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---help---
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Number of seconds to wait in PM_SLEEP.
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config PM_SLEEP_WAKEUP_NSEC
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int "PM_SLEEP delay (nanoseconds)"
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default 0
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depends on PM
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---help---
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Number of additional nanoseconds to wait in PM_SLEEP.
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endif # PM
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if ESP32_SPIRAM
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it
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based on hardware design. If user use 1.8V flash and 1.8V psram,
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this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based
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on hardware design. If user use 1.8V flash and 1.8V psram, this
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value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip,
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the psram can only be 1.8V psram, so this value can only be one
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of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on
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hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do
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not need to configure the clock IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config ESP32_SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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range 0 33
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default 7
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help
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This value is ignored unless flash mode is set to DIO or DOUT and
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the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4
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Quad I/O data pins. The WP pin (aka ESP32 pin "SD_DATA_3" or SPI
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flash pin "IO2") is not specified in eFuse. And the psram only
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has QPI mode, the WP pin is necessary, so we need to configure
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this value here.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be
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set as the value configured in bootloader.
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For ESP32-PICO chip, the default value of this config should be 7.
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endif # ESP32_PSRAM
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endif # ARCH_BOARD_ESP32_DEVKITC
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