4ebc581c73
ESP32C3 use customized irq encoding so it's hard to share further code with other risc-v based chips, in this patch, we keep the exception number definition with risc-v spec. Signed-off-by: Huang Qi <huangqi3@xiaomi.com> |
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| .. | ||
| chip.h | ||
| esp_efuse_table.h | ||
| irq.h | ||