037c9ea0a4
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private files begin with the name of the architecture, not up_. This PR addresses only these name changes for the up_*.h files. There are only three, but almost 1680 files that include them: up_arch.h up_internal.h up_vfork.h The only change to the files is from including up_arch.h to arm_arch.h (for example). The entire job required to be compatible with that Naming Convention will also require changing the naming of the up_() functions that are used only within arch/arm and board/arm. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
113 lines
4.0 KiB
C
113 lines
4.0 KiB
C
/****************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32g0_pwr.c
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Daniel Pereira Volpato <dpo@certi.org.br>
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*
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* Based on: arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "arm_arch.h"
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#include "stm32_pwr.h"
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#if defined(CONFIG_STM32F0L0G0_PWR)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static inline uint32_t stm32_pwr_getreg32(uint8_t offset)
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{
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return getreg32(STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value)
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{
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putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
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uint32_t setbits)
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{
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modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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void stm32_pwr_setvos(uint16_t vos)
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{
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uint16_t regval;
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/* The following sequence is required to program the voltage regulator
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* ranges:
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* 1. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2).
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* 2. Configure the voltage scaling range by setting the VOS bits in the
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* PWR_CR1 register.
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* 3. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2).
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*
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* No checking is performed to ensure the VOS value to be set is within the
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* valid range.
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*/
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while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0)
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{
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}
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regval = stm32_pwr_getreg32(STM32_PWR_CR1_OFFSET);
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regval &= ~PWR_CR1_VOS_MASK;
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regval |= (vos & PWR_CR1_VOS_MASK);
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stm32_pwr_putreg32(STM32_PWR_CR1_OFFSET, regval);
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while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0)
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{
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}
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}
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/* TODO Other stm32_pwr_* functions need to be implemented */
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#endif /* CONFIG_STM32F0L0G0_PWR */
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