802 lines
31 KiB
C
802 lines
31 KiB
C
/************************************************************************************
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* arch/arm/src/stm32L4/stm32l4_adc.h
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*
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* Copyright (C) 2009, 2011, 2015-2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Paul Alexander Patience <paul-a.patience@polymtl.ca>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/analog/adc.h>
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#include "chip.h"
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#include "hardware/stm32l4_adc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is to
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* control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then
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* CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is
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* intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on
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* STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well.
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*/
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#ifndef CONFIG_STM32L4_TIM1
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# undef CONFIG_STM32L4_TIM1_ADC
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# undef CONFIG_STM32L4_TIM1_ADC1
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# undef CONFIG_STM32L4_TIM1_ADC2
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# undef CONFIG_STM32L4_TIM1_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM2
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# undef CONFIG_STM32L4_TIM2_ADC
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# undef CONFIG_STM32L4_TIM2_ADC1
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# undef CONFIG_STM32L4_TIM2_ADC2
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# undef CONFIG_STM32L4_TIM2_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM3
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# undef CONFIG_STM32L4_TIM3_ADC
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# undef CONFIG_STM32L4_TIM3_ADC1
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# undef CONFIG_STM32L4_TIM3_ADC2
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# undef CONFIG_STM32L4_TIM3_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM4
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# undef CONFIG_STM32L4_TIM4_ADC
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# undef CONFIG_STM32L4_TIM4_ADC1
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# undef CONFIG_STM32L4_TIM4_ADC2
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# undef CONFIG_STM32L4_TIM4_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM6
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# undef CONFIG_STM32L4_TIM6_ADC
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# undef CONFIG_STM32L4_TIM6_ADC1
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# undef CONFIG_STM32L4_TIM6_ADC2
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# undef CONFIG_STM32L4_TIM6_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM8
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# undef CONFIG_STM32L4_TIM8_ADC
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# undef CONFIG_STM32L4_TIM8_ADC1
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# undef CONFIG_STM32L4_TIM8_ADC2
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# undef CONFIG_STM32L4_TIM8_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM15
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# undef CONFIG_STM32L4_TIM15_ADC
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# undef CONFIG_STM32L4_TIM15_ADC1
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# undef CONFIG_STM32L4_TIM15_ADC2
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# undef CONFIG_STM32L4_TIM15_ADC3
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#endif
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/* Up to 3 ADC interfaces are supported */
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#if STM32L4_NADC < 3
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# undef CONFIG_STM32L4_ADC3
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#endif
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#if STM32L4_NADC < 2
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# undef CONFIG_STM32L4_ADC2
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#endif
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#if STM32L4_NADC < 1
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# undef CONFIG_STM32L4_ADC1
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#endif
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#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \
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defined(CONFIG_STM32L4_ADC3)
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/* ADC output to DFSDM support. Note that DFSDM and DMA are
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* mutually exclusive.
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*/
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#undef ADC_HAVE_DFSDM
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#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \
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defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \
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defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM)
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# define ADC_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM)
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# define ADC1_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC1_DMA
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#else
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# undef ADC1_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM)
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# define ADC2_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC2_DMA
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#else
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# undef ADC2_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM)
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# define ADC3_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC3_DMA
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#else
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# undef ADC3_HAVE_DFSDM
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#endif
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/* DMA support */
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#undef ADC_HAVE_DMA
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#if defined(CONFIG_STM32L4_ADC1_DMA) || defined(CONFIG_STM32L4_ADC2_DMA) || \
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defined(CONFIG_STM32L4_ADC3_DMA)
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# define ADC_HAVE_DMA 1
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#endif
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#ifdef CONFIG_STM32L4_ADC1_DMA
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# define ADC1_HAVE_DMA 1
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#else
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# undef ADC1_HAVE_DMA
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#endif
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#ifdef CONFIG_STM32L4_ADC2_DMA
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# define ADC2_HAVE_DMA 1
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#else
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# undef ADC2_HAVE_DMA
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#endif
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#ifdef CONFIG_STM32L4_ADC3_DMA
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# define ADC3_HAVE_DMA 1
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#else
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# undef ADC3_HAVE_DMA
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#endif
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/* Timer configuration: If a timer trigger is specified, then get
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* information about the timer.
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*/
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#if defined(CONFIG_STM32L4_TIM1_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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#elif defined(CONFIG_STM32L4_TIM2_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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#elif defined(CONFIG_STM32L4_TIM3_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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#elif defined(CONFIG_STM32L4_TIM4_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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#elif defined(CONFIG_STM32L4_TIM6_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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#elif defined(CONFIG_STM32L4_TIM8_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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#elif defined(CONFIG_STM32L4_TIM15_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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#else
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# undef ADC1_HAVE_TIMER
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#endif
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#ifdef ADC1_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined"
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# endif
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# ifndef CONFIG_STM32L4_ADC1_TIMTRIG
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# error "CONFIG_STM32L4_ADC1_TIMTRIG not defined"
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# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
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# endif
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#endif
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#if defined(CONFIG_STM32L4_TIM1_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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#elif defined(CONFIG_STM32L4_TIM2_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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#elif defined(CONFIG_STM32L4_TIM3_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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#elif defined(CONFIG_STM32L4_TIM4_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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#elif defined(CONFIG_STM32L4_TIM6_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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#elif defined(CONFIG_STM32L4_TIM8_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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#elif defined(CONFIG_STM32L4_TIM15_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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#else
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# undef ADC2_HAVE_TIMER
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#endif
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#ifdef ADC2_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined"
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# endif
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# ifndef CONFIG_STM32L4_ADC2_TIMTRIG
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# error "CONFIG_STM32L4_ADC2_TIMTRIG not defined"
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# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
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# endif
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#endif
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#if defined(CONFIG_STM32L4_TIM1_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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#elif defined(CONFIG_STM32L4_TIM2_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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#elif defined(CONFIG_STM32L4_TIM3_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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#elif defined(CONFIG_STM32L4_TIM4_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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#elif defined(CONFIG_STM32L4_TIM6_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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#elif defined(CONFIG_STM32L4_TIM8_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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#elif defined(CONFIG_STM32L4_TIM15_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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#else
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# undef ADC3_HAVE_TIMER
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#endif
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#ifdef ADC3_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined"
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# endif
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# ifndef CONFIG_STM32L4_ADC3_TIMTRIG
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# error "CONFIG_STM32L4_ADC3_TIMTRIG not defined"
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# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
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# endif
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#endif
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#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \
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defined(ADC3_HAVE_TIMER)
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# define ADC_HAVE_TIMER 1
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#else
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# undef ADC_HAVE_TIMER
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#endif
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/* NOTE: The following assumes that all possible combinations of timers and
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* values are support EXTSEL. That is not so and it varies from one STM32
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* to another. But this (wrong) assumptions keeps the logic as simple as
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* possible. If unsupported combination is used, an error will show up
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* later during compilation although it may be difficult to track it back
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* to this simplification.
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*/
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#define ADC1_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
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#define ADC1_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
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#define ADC1_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
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#define ADC1_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
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#define ADC1_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
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#define ADC1_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
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#define ADC2_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
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#define ADC2_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
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#define ADC2_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
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#define ADC2_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
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#define ADC2_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
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#define ADC2_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
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#define ADC3_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
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#define ADC3_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
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#define ADC3_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
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#define ADC3_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
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#define ADC3_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
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#define ADC3_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
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#define ADC1_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
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#define ADC1_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
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#define ADC1_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
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#define ADC1_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
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#define ADC1_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
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#define ADC2_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
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#define ADC2_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
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#define ADC2_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
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#define ADC2_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
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#define ADC2_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
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#define ADC3_EXTSEL_T2CC1 ADC_CFGR_EXTSEL_T2CC1
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#define ADC3_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
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#define ADC3_EXTSEL_T2CC3 ADC_CFGR_EXTSEL_T2CC3
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#define ADC3_EXTSEL_T2CC4 ADC_CFGR_EXTSEL_T2CC4
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#define ADC3_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
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#define ADC1_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
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#define ADC1_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
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#define ADC1_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
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#define ADC1_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
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#define ADC1_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
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#define ADC2_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
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#define ADC2_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
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#define ADC2_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
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#define ADC2_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
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#define ADC2_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
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#define ADC3_EXTSEL_T3CC1 ADC_CFGR_EXTSEL_T3CC1
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#define ADC3_EXTSEL_T3CC2 ADC_CFGR_EXTSEL_T3CC2
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#define ADC3_EXTSEL_T3CC3 ADC_CFGR_EXTSEL_T3CC3
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#define ADC3_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
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#define ADC3_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
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#define ADC1_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
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#define ADC1_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
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#define ADC1_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
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#define ADC1_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
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#define ADC1_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
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#define ADC2_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
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#define ADC2_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
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#define ADC2_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
|
|
#define ADC2_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
|
|
#define ADC2_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
|
|
#define ADC3_EXTSEL_T4CC1 ADC_CFGR_EXTSEL_T4CC1
|
|
#define ADC3_EXTSEL_T4CC2 ADC_CFGR_EXTSEL_T4CC2
|
|
#define ADC3_EXTSEL_T4CC3 ADC_CFGR_EXTSEL_T4CC3
|
|
#define ADC3_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
|
|
#define ADC3_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
|
|
|
|
#define ADC1_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
|
|
#define ADC1_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
|
|
#define ADC1_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
|
|
#define ADC1_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
|
|
#define ADC1_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
|
|
#define ADC2_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
|
|
#define ADC2_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
|
|
#define ADC2_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
|
|
#define ADC2_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
|
|
#define ADC2_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
|
|
#define ADC3_EXTSEL_T6CC1 ADC_CFGR_EXTSEL_T6CC1
|
|
#define ADC3_EXTSEL_T6CC2 ADC_CFGR_EXTSEL_T6CC2
|
|
#define ADC3_EXTSEL_T6CC3 ADC_CFGR_EXTSEL_T6CC3
|
|
#define ADC3_EXTSEL_T6CC4 ADC_CFGR_EXTSEL_T6CC4
|
|
#define ADC3_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
|
|
|
|
#define ADC1_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
|
|
#define ADC1_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
|
|
#define ADC1_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
|
|
#define ADC1_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
|
|
#define ADC1_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
|
|
#define ADC1_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
|
|
#define ADC2_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
|
|
#define ADC2_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
|
|
#define ADC2_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
|
|
#define ADC2_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
|
|
#define ADC2_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
|
|
#define ADC2_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
|
|
#define ADC3_EXTSEL_T8CC1 ADC_CFGR_EXTSEL_T8CC1
|
|
#define ADC3_EXTSEL_T8CC2 ADC_CFGR_EXTSEL_T8CC2
|
|
#define ADC3_EXTSEL_T8CC3 ADC_CFGR_EXTSEL_T8CC3
|
|
#define ADC3_EXTSEL_T8CC4 ADC_CFGR_EXTSEL_T8CC4
|
|
#define ADC3_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
|
|
#define ADC3_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
|
|
|
|
#define ADC1_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
|
|
#define ADC1_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
|
|
#define ADC1_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
|
|
#define ADC1_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
|
|
#define ADC1_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
|
|
#define ADC2_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
|
|
#define ADC2_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
|
|
#define ADC2_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
|
|
#define ADC2_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
|
|
#define ADC2_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
|
|
#define ADC3_EXTSEL_T15CC1 ADC_CFGR_EXTSEL_T15CC1
|
|
#define ADC3_EXTSEL_T15CC2 ADC_CFGR_EXTSEL_T15CC2
|
|
#define ADC3_EXTSEL_T15CC3 ADC_CFGR_EXTSEL_T15CC3
|
|
#define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
|
|
#define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
|
|
|
|
|
|
#if defined(CONFIG_STM32L4_TIM1_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 5
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM2_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM3_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM4_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM6_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM8_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 5
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM15_ADC1)
|
|
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 1
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 2
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 3
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4
|
|
# elif CONFIG_STM32L4_ADC1_TIMTRIG == 4
|
|
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
|
# endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_STM32L4_TIM1_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 5
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM2_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM3_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM4_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM6_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM8_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 5
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM15_ADC2)
|
|
# if CONFIG_STM32L4_ADC2_TIMTRIG == 0
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 1
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 2
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 3
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4
|
|
# elif CONFIG_STM32L4_ADC2_TIMTRIG == 4
|
|
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
|
# endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_STM32L4_TIM1_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 5
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM2_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM3_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM4_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM6_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
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# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1
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# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM8_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 5
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#elif defined(CONFIG_STM32L4_TIM15_ADC3)
|
|
# if CONFIG_STM32L4_ADC3_TIMTRIG == 0
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 1
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 2
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 3
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4
|
|
# elif CONFIG_STM32L4_ADC3_TIMTRIG == 4
|
|
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO
|
|
# else
|
|
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
|
# endif
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Types
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Function Prototypes
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32l4_adc_initialize
|
|
*
|
|
* Description:
|
|
* Initialize the ADC.
|
|
*
|
|
* Input Parameters:
|
|
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
|
|
* chanlist - The list of channels
|
|
* nchannels - Number of channels
|
|
*
|
|
* Returned Value:
|
|
* Valid ADC device structure reference on success; a NULL on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
struct adc_dev_s;
|
|
struct adc_dev_s *stm32l4_adc_initialize(int intf,
|
|
FAR const uint8_t *chanlist,
|
|
int nchannels);
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */
|
|
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */
|