e77b06721b
N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
35 lines
1.4 KiB
C
35 lines
1.4 KiB
C
/****************************************************************************
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* arch/arm64/include/qemu/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM64_INCLUDE_QEMU_IRQ_H
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#define __ARCH_ARM64_INCLUDE_QEMU_IRQ_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NR_IRQS 220 /* Total number of interrupts */
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#endif /* __ARCH_ARM64_INCLUDE_QEMU_IRQ_H */
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