173 lines
7.9 KiB
C
173 lines
7.9 KiB
C
/****************************************************************************************
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* arch/arm/include/tms570/tms570ls04x03x_irq.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_TMS570_TMS570LS04X03X_IRQ_H
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#define __ARCH_ARM_INCLUDE_TMS570_TMS570LS04X03X_IRQ_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* The interrupt vector table only has 96 entries, one phantom vector and 95 interrupt
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* channels. Channel 95 does not have a dedicated vector and shall not be used.
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*/
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#define TMS570_IRQ_NCHANNELS 95 /* The "phantom" vector is followed by 95 real
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* interrupt channels */
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/* Default request to channel assignments. Undefined requests are reserved */
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#define TMS570_REQ_ESMHIGH 0 /* ESM High level interrupt (NMI) */
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#define TMS570_REQ_RTICMP0 2 /* RTI compare interrupt 0 */
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#define TMS570_REQ_RTICMP1 3 /* RTI compare interrupt 1 */
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#define TMS570_REQ_RTICMP2 4 /* RTI compare interrupt 2 */
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#define TMS570_REQ_RTICMP3 5 /* RTI compare interrupt 3 */
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#define TMS570_REQ_RTIOVF0 6 /* RTI overflow interrupt 0 */
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#define TMS570_REQ_RTIOVF1 7 /* RTI overflow interrupt 1 */
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#define TMS570_REQ_GIO_0 9 /* GIO level 0 interrupt */
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#define TMS570_REQ_N2HET_0 10 /* N2HET level 0 interrupt */
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#define TMS570_REQ_HTU_0 11 /* HTU level 0 interrupt */
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#define TMS570_REQ_MIBSPI1_0 12 /* MIBSPI1 level 0 interrupt */
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#define TMS570_REQ_SCI1_0 13 /* SCI1/LIN1 level 0 interrupt */
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#define TMS570_REQ_MIBADCEV 14 /* MIBADC event group interrupt */
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#define TMS570_REQ_MIBADSW1 15 /* MIBADC sw group 1 interrupt */
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#define TMS570_REQ_DCAN1_0 16 /* DCAN1 level 0 interrupt */
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#define TMS570_REQ_SPI2_0 17 /* SPI2 level 0 interrupt */
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#define TMS570_REQ_ESMLO 20 /* ESM Low level interrupt */
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#define TMS570_REQ_SYSTEM 21 /* Software interrupt (SSI) */
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#define TMS570_REQ_CPU 22 /* PMU interrupt */
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#define TMS570_REQ_GIO_1 23 /* GIO level 1 interrupt */
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#define TMS570_REQ_N2HET_1 24 /* N2HET level 1 interrupt */
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#define TMS570_REQ_HTU_1 25 /* HTU level 1 interrupt */
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#define TMS570_REQ_MIBSPI1_1 26 /* MIBSPI1 level 1 interrupt */
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#define TMS570_REQ_SCI1_1 27 /* SCI1/LIN1 level 1 interrupt */
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#define TMS570_REQ_MIBADCSW2 28 /* MIBADC sw group 2 interrupt */
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#define TMS570_REQ_DCAN1_1 29 /* DCAN1 level 1 interrupt */
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#define TMS570_REQ_SPI2_1 30 /* SPI2 level 1 interrupt */
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#define TMS570_REQ_MIBADCMC 31 /* MIBADC magnitude compare interrupt */
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#define TMS570_REQ_DCAN2_0 35 /* DCAN2 level 0 interrupt */
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#define TMS570_REQ_SPI3_0 37 /* SPI3 level 0 interrupt */
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#define TMS570_REQ_SPI3_1 38 /* SPI3 level 1 interrupt */
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#define TMS570_REQ_DCAN2_1 42 /* DCAN2 level 1 interrupt */
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#define TMS570_REQ_FMC 61 /* FSM_DONE interrupt */
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#define TMS570_REQ_HWAGH 80 /* WA_INT_REQ_H */
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#define TMS570_REQ_DCC 82 /* DCC done interrupt */
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#define TMS570_REQ_EQEP 84 /* eQEP Interrupt */
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#define TMS570_REQ_PBIST 85 /* PBIST Done Interrupt */
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#define TMS570_REQ_HWAGL 88 /* HWA_INT_REQ_L */
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#ifdef CONFIG_TMS570_GIO_IRQ
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# define TMS570_IRQ_GIOA0 (TMS570_IRQ_NCHANNELS+1)
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# define TMS570_IRQ_GIOA1 (TMS570_IRQ_NCHANNELS+2)
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# define TMS570_IRQ_GIOA2 (TMS570_IRQ_NCHANNELS+3)
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# define TMS570_IRQ_GIOA3 (TMS570_IRQ_NCHANNELS+4)
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# define TMS570_IRQ_GIOA4 (TMS570_IRQ_NCHANNELS+5)
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# define TMS570_IRQ_GIOA5 (TMS570_IRQ_NCHANNELS+6)
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# define TMS570_IRQ_GIOA6 (TMS570_IRQ_NCHANNELS+7)
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# define TMS570_IRQ_GIOA7 (TMS570_IRQ_NCHANNELS+8)
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# define TMS570_IRQ_GIOB0 (TMS570_IRQ_NCHANNELS+9)
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# define TMS570_IRQ_GIOB1 (TMS570_IRQ_NCHANNELS+10)
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# define TMS570_IRQ_GIOB2 (TMS570_IRQ_NCHANNELS+11)
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# define TMS570_IRQ_GIOB3 (TMS570_IRQ_NCHANNELS+12)
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# define TMS570_IRQ_GIOB4 (TMS570_IRQ_NCHANNELS+13)
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# define TMS570_IRQ_GIOB5 (TMS570_IRQ_NCHANNELS+14)
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# define TMS570_IRQ_GIOB6 (TMS570_IRQ_NCHANNELS+15)
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# define TMS570_IRQ_GIOB7 (TMS570_IRQ_NCHANNELS+16)
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# define TMS570_IRQ_GIOC0 (TMS570_IRQ_NCHANNELS+17)
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# define TMS570_IRQ_GIOC1 (TMS570_IRQ_NCHANNELS+18)
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# define TMS570_IRQ_GIOC2 (TMS570_IRQ_NCHANNELS+19)
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# define TMS570_IRQ_GIOC3 (TMS570_IRQ_NCHANNELS+20)
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# define TMS570_IRQ_GIOC4 (TMS570_IRQ_NCHANNELS+21)
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# define TMS570_IRQ_GIOC5 (TMS570_IRQ_NCHANNELS+22)
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# define TMS570_IRQ_GIOC6 (TMS570_IRQ_NCHANNELS+23)
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# define TMS570_IRQ_GIOC7 (TMS570_IRQ_NCHANNELS+24)
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# define TMS570_IRQ_GIOD0 (TMS570_IRQ_NCHANNELS+25)
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# define TMS570_IRQ_GIOD1 (TMS570_IRQ_NCHANNELS+26)
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# define TMS570_IRQ_GIOD2 (TMS570_IRQ_NCHANNELS+27)
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# define TMS570_IRQ_GIOD3 (TMS570_IRQ_NCHANNELS+28)
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# define TMS570_IRQ_GIOD4 (TMS570_IRQ_NCHANNELS+29)
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# define TMS570_IRQ_GIOD5 (TMS570_IRQ_NCHANNELS+30)
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# define TMS570_IRQ_GIOD6 (TMS570_IRQ_NCHANNELS+31)
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# define TMS570_IRQ_GIOD7 (TMS570_IRQ_NCHANNELS+32)
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# define TMS570_NGIO_IRQS 32
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#else
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# define TMS570_NGIO_IRQS 0
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#endif
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************
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* Public Function Prototypes
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****************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_TMS570_TMS570LS04X03X_IRQ_H */
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