zhongan 07dd053e86 risc-v: add putreg64 for mtimer registers. ... Change-Id: I18fe312c95c73966f5c09fd18081b0c72923e2ac Signed-off-by: zhongan <zhongan@xiaomi.com>		2020-09-23 10:22:45 +01:00
..
include	Add and fix CSR macros listed in RISC-V spec V1.10.	2020-09-21 07:35:56 -07:00
src	risc-v: add putreg64 for mtimer registers.	2020-09-23 10:22:45 +01:00
Kconfig	arch, include, sched : Refactor ARCH_GLOBAL_IRQDISABLE related code	2020-09-03 10:20:20 +08:00