208 lines
8.6 KiB
C
208 lines
8.6 KiB
C
/****************************************************************************
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* arch/arm/include/a1x/a10_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
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#define __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* External interrupts numbers */
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#define A1X_IRQ_NMI 0 /* External Non-Mask Interrupt */
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# define A1X_IRQ_POWER 0 /* Power module */
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# define A1X_IRQ_BATTERY 0 /* Brownout detect */
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# define A1X_IRQ_BROWNOUT 0 /* Brownout */
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#define A1X_IRQ_UART0 1 /* UART 0 interrupt */
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#define A1X_IRQ_UART1 2 /* UART 1 interrupt */
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#define A1X_IRQ_UART2 3 /* UART 2 interrupt */
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#define A1X_IRQ_UART3 4 /* UART 3 interrupt */
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#define A1X_IRQ_IR0 5 /* IR 0 interrupt */
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#define A1X_IRQ_IR1 6 /* IR 1 interrupt */
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#define A1X_IRQ_TWI0 7 /* TWI 0 interrupt */
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#define A1X_IRQ_TWI1 8 /* TWI 1 interrupt */
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#define A1X_IRQ_TWI2 9 /* TWI 2 interrupt */
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#define A1X_IRQ_SPI0 10 /* SPI 0 interrupt */
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#define A1X_IRQ_SPI1 11 /* SPI 1 interrupt */
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#define A1X_IRQ_SPI2 12 /* SPI 2 interrupt */
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#define A1X_IRQ_NC 13 /* NC */
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#define A1X_IRQ_AC97 14 /* AC97 interrupt */
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#define A1X_IRQ_TS 15 /* TS interrupt */
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#define A1X_IRQ_IIS 16 /* Digital Audio Controller interrupt */
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#define A1X_IRQ_UART4 17 /* UART 4 interrupt */
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#define A1X_IRQ_UART5 18 /* UART 5 interrupt */
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#define A1X_IRQ_UART6 19 /* UART 6 interrupt */
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#define A1X_IRQ_UART7 20 /* UART 7 interrupt */
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#define A1X_IRQ_KEYPAD 21 /* Keypad interrupt */
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#define A1X_IRQ_TIMER0 22 /* Timer port 0 */
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#define A1X_IRQ_TIMER1 23 /* Timer port 1 */
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#define A1X_IRQ_TIMER2 24 /* Timer 2 */
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# define A1X_IRQ_ALARM 24 /* Alarm */
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# define A1X_IRQ_WD 24 /* Watchdog */
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#define A1X_IRQ_TIMER3 25 /* Timer 3 interrupt */
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#define A1X_IRQ_CAN 26 /* CAN Bus controller interrupt */
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#define A1X_IRQ_DMA 27 /* DMA channel interrupt */
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#define A1X_IRQ_PIO 28 /* PIO interrupt */
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#define A1X_IRQ_TOUCH 29 /* Touch Panel interrupt */
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#define A1X_IRQ_AUDIO 30 /* Analog Audio Codec interrupt */
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#define A1X_IRQ_LRADC 31 /* LRADC interrupt */
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#define A1X_IRQ_SDMMC0 32 /* SD/MMC Host Controller 0 interrupt */
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#define A1X_IRQ_SDMMC1 33 /* SD/MMC Host Controller 1 interrupt */
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#define A1X_IRQ_SDMMC2 34 /* SD/MMC Host Controller 2 interrupt */
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#define A1X_IRQ_SDMMC3 35 /* SD/MMC Host Controller 3 interrupt */
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#define A1X_IRQ_RESERVED36 36
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#define A1X_IRQ_NAND 37 /* NAND Flash Controller (NFC) interrupt */
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#define A1X_IRQ_USB0 38 /* USB 0 wakeup, connect, disconnect interrupt */
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#define A1X_IRQ_USB1 39 /* USB 1 wakeup, connect, disconnect interrupt */
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#define A1X_IRQ_USB2 40 /* USB 2 wakeup, connect, disconnect interrupt */
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#define A1X_IRQ_SCR 41 /* SCR interrupt */
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#define A1X_IRQ_CSI0 42 /* CSI 0 interrupt */
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#define A1X_IRQ_CSI1 43 /* CSI 1 interrupt */
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#define A1X_IRQ_LCDC0 44 /* LCD Controller 0 interrupt */
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#define A1X_IRQ_LCDC1 45 /* LCD Controller 1 interrupt */
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#define A1X_IRQ_MP 46 /* MP interrupt */
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#define A1X_IRQ_DEFE0 47 /* DE-FE0 interrupt */
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# define A1X_IRQ_DEBE0 47 /* DE-BE0 interrupt */
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#define A1X_IRQ_DEFE1 48 /* DE-FE1 interrupt */
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# define A1X_IRQ_DEBE1 48 /* DE-BE1 interrupt */
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#define A1X_IRQ_PMU 49 /* PMU interrupt */
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#define A1X_IRQ_SPI3 50 /* SPI3 interrupt */
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#define A1X_IRQ_TZASC 51 /* TZASC interrupt */
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#define A1X_IRQ_PATA 52 /* PATA interrupt */
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#define A1X_IRQ_VE 53 /* VE interrupt */
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#define A1X_IRQ_SS 54 /* Security System interrupt */
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#define A1X_IRQ_EMAC 55 /* EMAC interrupt */
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#define A1X_IRQ_RESERVED56 56
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#define A1X_IRQ_RESERVED57 57
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#define A1X_IRQ_HDMI 58 /* HDMI interrupt */
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#define A1X_IRQ_TVE 59 /* TV encoder 0/1 interrupt */
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#define A1X_IRQ_ACE 60 /* ACE interrupt */
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#define A1X_IRQ_TVD 61 /* TV decoder interrupt */
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#define A1X_IRQ_PS20 62 /* PS2-0 interrupt */
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#define A1X_IRQ_PS21 63 /* PS2-1 interrupt */
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#define A1X_IRQ_USB3 64 /* USB 3 wakeup, connect, disconnect interrupt */
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#define A1X_IRQ_USB4 65 /* USB 4 wakeup, connect, disconnect interrupt */
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#define A1X_IRQ_PLE 66 /* PLE interrupts */
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# define A1X_IRQ_PERFMU 66 /* Performance monitor interrupt */
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#define A1X_IRQ_TIMER4 67 /* Timer 4 interrupt */
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#define A1X_IRQ_TIMER5 68 /* Timer 5 interrupt */
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#define A1X_IRQ_GPU_GP 69
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#define A1X_IRQ_GPU_GPMMU 70
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#define A1X_IRQ_GPU_PP0 71
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#define A1X_IRQ_GPU_PPMMU0 72
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#define A1X_IRQ_GPU_PMU 73
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#define A1X_IRQ_GPU_RSV0 74
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#define A1X_IRQ_GPU_RSV1 75
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#define A1X_IRQ_GPU_RSV2 76
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#define A1X_IRQ_GPU_RSV3 77
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#define A1X_IRQ_GPU_RSV4 78
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#define A1X_IRQ_GPU_RSV5 79
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#define A1X_IRQ_GPU_RSV6 80
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/* Total number of interrupts */
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#define A1X_IRQ_NINT 81
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/* Up to 32 external PIO interrupts */
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#ifdef CONFIG_A1X_PIO_IRQ
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# define A1X_PIO_EINT0 (A1X_IRQ_NINT+0)
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# define A1X_PIO_EINT1 (A1X_IRQ_NINT+1)
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# define A1X_PIO_EINT2 (A1X_IRQ_NINT+2)
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# define A1X_PIO_EINT3 (A1X_IRQ_NINT+3)
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# define A1X_PIO_EINT4 (A1X_IRQ_NINT+4)
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# define A1X_PIO_EINT5 (A1X_IRQ_NINT+5)
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# define A1X_PIO_EINT6 (A1X_IRQ_NINT+6)
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# define A1X_PIO_EINT7 (A1X_IRQ_NINT+7)
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# define A1X_PIO_EINT8 (A1X_IRQ_NINT+8)
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# define A1X_PIO_EINT9 (A1X_IRQ_NINT+9)
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# define A1X_PIO_EINT10 (A1X_IRQ_NINT+10)
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# define A1X_PIO_EINT11 (A1X_IRQ_NINT+11)
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# define A1X_PIO_EINT12 (A1X_IRQ_NINT+12)
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# define A1X_PIO_EINT13 (A1X_IRQ_NINT+13)
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# define A1X_PIO_EINT14 (A1X_IRQ_NINT+14)
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# define A1X_PIO_EINT15 (A1X_IRQ_NINT+15)
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# define A1X_PIO_EINT16 (A1X_IRQ_NINT+16)
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# define A1X_PIO_EINT17 (A1X_IRQ_NINT+17)
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# define A1X_PIO_EINT18 (A1X_IRQ_NINT+18)
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# define A1X_PIO_EINT19 (A1X_IRQ_NINT+19)
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# define A1X_PIO_EINT20 (A1X_IRQ_NINT+20)
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# define A1X_PIO_EINT21 (A1X_IRQ_NINT+21)
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# define A1X_PIO_EINT22 (A1X_IRQ_NINT+22)
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# define A1X_PIO_EINT23 (A1X_IRQ_NINT+23)
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# define A1X_PIO_EINT24 (A1X_IRQ_NINT+24)
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# define A1X_PIO_EINT25 (A1X_IRQ_NINT+25)
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# define A1X_PIO_EINT26 (A1X_IRQ_NINT+26)
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# define A1X_PIO_EINT27 (A1X_IRQ_NINT+27)
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# define A1X_PIO_EINT28 (A1X_IRQ_NINT+28)
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# define A1X_PIO_EINT29 (A1X_IRQ_NINT+29)
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# define A1X_PIO_EINT30 (A1X_IRQ_NINT+30)
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# define A1X_PIO_EINT31 (A1X_IRQ_NINT+31)
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# define A1X_PIO_NINT 32
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#else
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# define A1X_PIO_NINT 0
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#endif
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/* Total number of IRQ numbers */
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#define NR_IRQS (A1X_IRQ_NINT + A1X_PIO_NINT)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H */
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