0841f4dbaa
Summary: Adding armv8-r(Cortex-R82) support and modify some common code to fit the change, the change including: 1. ARM Single Security State Support, ARMv8-R support only single security state, and some GIC configure need to change and fit 2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary and system register for EL3 is not accessible(gcc will failed when access these registers) 3. add base MPU configure for the platform. Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
187 lines
4.1 KiB
Plaintext
187 lines
4.1 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_ARM64
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comment "ARM64 Options"
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choice
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prompt "ARM64 Toolchain Selection"
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default ARM64_TOOLCHAIN_GNU_EABI
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config ARM64_TOOLCHAIN_GNU_EABI
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bool "Generic GNU EABI toolchain"
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 4.5 or newer)
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config ARM64_TOOLCHAIN_CLANG
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bool "LLVM Clang toolchain"
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select ARCH_TOOLCHAIN_CLANG
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endchoice
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choice
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prompt "ARM64 chip selection"
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default ARCH_CHIP_QEMU
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config ARCH_CHIP_A64
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bool "Allwinner A64"
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select ARCH_CORTEX_A53
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_RESET
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select ARCH_HAVE_PSCI
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Allwinner A64 SoC
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config ARCH_CHIP_QEMU
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bool "QEMU virt platform (ARMv8a)"
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select ARCH_CORTEX_A53
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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QEMU virt platform (ARMv8a)
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endchoice
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config ARCH_ARMV8A
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bool
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default n
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select ARCH_HAVE_EL3
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config ARCH_ARMV8R
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bool
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default n
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select ARCH_SINGLE_SECURITY_STATE
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config ARCH_HAVE_PSCI
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bool "ARM PCSI (Power State Coordination Interface) Support"
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default n
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---help---
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This Power State Coordination Interface (PSCI) defines
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a standard interface for power management. the PCSI need
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to implement handling firmware at EL2 or EL3. The option
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maybe not applicable for arm core without PCSI firmware
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interface implement
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config ARCH_SINGLE_SECURITY_STATE
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bool "ARM Single Security State Support"
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default n
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---help---
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Some ARM aarch64 Cortex-family processors only supports single
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security state(eg. Cortex-R82). For these Processors,
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GIC or other ARM architecture feature will with different
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configure
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config ARCH_HAVE_EL3
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bool
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default n
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---help---
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Some ARM aarch64 Cortex-family processors only supports
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EL0~El2(eg. Cortex-R82). For these Processors, the code
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runing at EL3 is not necessary and system register for EL3
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is not accessible
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config ARCH_EARLY_PRINT
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bool "arch early print support"
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default n
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---help---
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The aarch64 have EL0~El3 execute level and NS/S (security state),
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the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
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state. but booting NuttX have different ELs and state while with
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different platform, if NuttX runing at wrong ELs or state it will
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be not normal anymore. So we need to print something in arm64_head.S
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to debug this situation.
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Enabling this option will need to implement up_earlyserialinit and
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up_lowputc functions just you see in qemu, if you not sure,
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keeping the option disable.
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config ARCH_CORTEX_A53
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bool
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default n
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select ARCH_ARMV8A
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select ARM_HAVE_NEON
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEX_A57
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bool
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default n
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select ARCH_ARMV8A
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select ARM_HAVE_NEON
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEX_A72
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bool
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default n
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select ARCH_ARMV8A
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select ARM_HAVE_NEON
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select ARCH_HAVE_TRUSTZONE
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEX_R82
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bool
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default n
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select ARCH_ARMV8R
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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config ARCH_FAMILY
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string
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default "armv8-a" if ARCH_ARMV8A
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default "armv8-r" if ARCH_ARMV8R
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config ARCH_CHIP
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string
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default "a64" if ARCH_CHIP_A64
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default "qemu" if ARCH_CHIP_QEMU
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config ARCH_HAVE_TRUSTZONE
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bool
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default n
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---help---
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Automatically selected to indicate that the ARM CPU supports
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TrustZone.
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config ARM_HAVE_NEON
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bool
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default n
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---help---
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Decide whether support NEON instruction
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config ARM_GIC_VERSION
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int "GIC version"
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default 2 if ARCH_CHIP_A64
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default 3
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range 2 4
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---help---
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Version of Generic Interrupt Controller (GIC) supported by the
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architecture
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if ARCH_CHIP_A64
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source "arch/arm64/src/a64/Kconfig"
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endif
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if ARCH_CHIP_QEMU
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source "arch/arm64/src/qemu/Kconfig"
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endif
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endif # ARCH_ARM64
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