08c4376606
Summary: - ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP - At that time, i.MX6 (quad Cortex-A9) did not use this config - However, this option is now used for all CPUs which support SMP - So it's good timing for refactoring the code Impact: - Should have no impact because the logic is the same for SMP Testing: - Tested with board: spresense:smp, spresense:wifi_smp - Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp - Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
63 lines
2.2 KiB
Plaintext
63 lines
2.2 KiB
Plaintext
############################################################################
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# sched/irq/Make.defs
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#
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# Copyright (C) 2014, 2016, 2018 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# 3. Neither the name NuttX nor the names of its contributors may be
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# used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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CSRCS += irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c
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ifeq ($(CONFIG_SMP),y)
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ifeq ($(CONFIG_SPINLOCK_IRQ),y)
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CSRCS += irq_spinlock.c
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endif
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endif
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ifeq ($(CONFIG_IRQCOUNT),y)
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CSRCS += irq_csection.c
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endif
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ifeq ($(CONFIG_SCHED_IRQMONITOR),y)
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CSRCS += irq_foreach.c
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ifeq ($(CONFIG_FS_PROCFS),y)
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CSRCS += irq_procfs.c
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endif
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endif
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ifeq ($(CONFIG_IRQCHAIN),y)
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CSRCS += irq_chain.c
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endif
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# Include irq build support
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DEPPATH += --dep-path irq
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VPATH += :irq
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