395 lines
14 KiB
C
395 lines
14 KiB
C
/****************************************************************************
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* arch/risc-v/include/csr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_RISCV_INCLUDE_CSR_H
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#define __ARCH_RISCV_INCLUDE_CSR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* User Trap Registers */
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#define CSR_USTATUS 0x000
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#define CSR_UIE 0x004
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#define CSR_UTVEC 0x005
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/* User Trap Handling Registers */
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#define CSR_USCRATCH 0x040
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#define CSR_UEPC 0x041
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#define CSR_UCAUSE 0x042
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#define CSR_UTVAL 0x043
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#define CSR_UIP 0x044
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/* User Floating-Point Registers */
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#define CSR_FFLAGS 0x001
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#define CSR_FRM 0x002
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#define CSR_FCSR 0x003
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/* User Counter/Times Registers */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPCOUNTER3 0xc03
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#define CSR_HPCOUNTER4 0xc04
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#define CSR_HPCOUNTER5 0xc05
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#define CSR_HPCOUNTER6 0xc06
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#define CSR_HPCOUNTER7 0xc07
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#define CSR_HPCOUNTER8 0xc08
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#define CSR_HPCOUNTER9 0xc09
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#define CSR_HPCOUNTER10 0xc0a
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#define CSR_HPCOUNTER11 0xc0b
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#define CSR_HPCOUNTER12 0xc0c
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#define CSR_HPCOUNTER13 0xc0d
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#define CSR_HPCOUNTER14 0xc0e
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#define CSR_HPCOUNTER15 0xc0f
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#define CSR_HPCOUNTER16 0xc10
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#define CSR_HPCOUNTER17 0xc11
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#define CSR_HPCOUNTER18 0xc12
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#define CSR_HPCOUNTER19 0xc13
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#define CSR_HPCOUNTER20 0xc14
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#define CSR_HPCOUNTER21 0xc15
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#define CSR_HPCOUNTER22 0xc16
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#define CSR_HPCOUNTER24 0xc17
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#define CSR_HPCOUNTER25 0xc18
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#define CSR_HPCOUNTER26 0xc19
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#define CSR_HPCOUNTER27 0xc1a
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#define CSR_HPCOUNTER28 0xc1b
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#define CSR_HPCOUNTER29 0xc1c
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#define CSR_HPCOUNTER30 0xc1d
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#define CSR_HPCOUNTER31 0xc1f
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPCOUNTER3H 0xc83
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#define CSR_HPCOUNTER4H 0xc84
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#define CSR_HPCOUNTER5H 0xc85
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#define CSR_HPCOUNTER6H 0xc86
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#define CSR_HPCOUNTER7H 0xc87
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#define CSR_HPCOUNTER8H 0xc88
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#define CSR_HPCOUNTER9H 0xc89
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#define CSR_HPCOUNTER10H 0xc8a
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#define CSR_HPCOUNTER11H 0xc8b
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#define CSR_HPCOUNTER12H 0xc8c
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#define CSR_HPCOUNTER13H 0xc8d
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#define CSR_HPCOUNTER14H 0xc8e
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#define CSR_HPCOUNTER15H 0xc8f
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#define CSR_HPCOUNTER16H 0xc90
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#define CSR_HPCOUNTER17H 0xc91
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#define CSR_HPCOUNTER18H 0xc92
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#define CSR_HPCOUNTER19H 0xc93
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#define CSR_HPCOUNTER20H 0xc94
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#define CSR_HPCOUNTER21H 0xc95
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#define CSR_HPCOUNTER22H 0xc96
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#define CSR_HPCOUNTER24H 0xc97
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#define CSR_HPCOUNTER25H 0xc98
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#define CSR_HPCOUNTER26H 0xc99
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#define CSR_HPCOUNTER27H 0xc9a
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#define CSR_HPCOUNTER28H 0xc9b
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#define CSR_HPCOUNTER29H 0xc9c
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#define CSR_HPCOUNTER30H 0xc9d
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#define CSR_HPCOUNTER31H 0xc9f
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/* Supervisor Trap Setup Registers */
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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/* Supervisor Trap Handling Registers */
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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/* Supervisor Protection and Translation Registers */
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#define CSR_SATP 0x180
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/* Machine Information Registers */
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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/* Machine Trap Registers */
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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/* Machine Trap Handling */
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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/* Machine Protection and Translation */
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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/* Machine Timers and Counters */
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MHPMCOUNTER3 0xb03
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#define CSR_MHPMCOUNTER4 0xb04
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#define CSR_MHPMCOUNTER5 0xb05
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#define CSR_MHPMCOUNTER6 0xb06
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#define CSR_MHPMCOUNTER7 0xb07
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#define CSR_MHPMCOUNTER8 0xb08
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#define CSR_MHPMCOUNTER9 0xb09
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#define CSR_MHPMCOUNTER10 0xb0a
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#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MCYCLEH 0xb80
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#define CSR_MINSTRETH 0xb82
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#define CSR_MHPMCOUNTER3H 0xb83
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#define CSR_MHPMCOUNTER4H 0xb84
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#define CSR_MHPMCOUNTER5H 0xb85
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#define CSR_MHPMCOUNTER6H 0xb86
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#define CSR_MHPMCOUNTER7H 0xb87
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#define CSR_MHPMCOUNTER8H 0xb88
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#define CSR_MHPMCOUNTER9H 0xb89
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#define CSR_MHPMCOUNTER10H 0xb8a
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#define CSR_MHPMCOUNTER11H 0xb8b
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#define CSR_MHPMCOUNTER12H 0xb8c
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#define CSR_MHPMCOUNTER13H 0xb8d
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#define CSR_MHPMCOUNTER14H 0xb8e
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#define CSR_MHPMCOUNTER15H 0xb8f
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#define CSR_MHPMCOUNTER16H 0xb90
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#define CSR_MHPMCOUNTER17H 0xb91
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#define CSR_MHPMCOUNTER18H 0xb92
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#define CSR_MHPMCOUNTER19H 0xb93
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#define CSR_MHPMCOUNTER20H 0xb94
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#define CSR_MHPMCOUNTER21H 0xb95
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#define CSR_MHPMCOUNTER22H 0xb96
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#define CSR_MHPMCOUNTER23H 0xb97
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#define CSR_MHPMCOUNTER24H 0xb98
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#define CSR_MHPMCOUNTER25H 0xb99
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#define CSR_MHPMCOUNTER26H 0xb9a
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#define CSR_MHPMCOUNTER27H 0xb9b
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#define CSR_MHPMCOUNTER28H 0xb9c
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#define CSR_MHPMCOUNTER29H 0xb9d
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#define CSR_MHPMCOUNTER30H 0xb9e
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#define CSR_MHPMCOUNTER31H 0xb9f
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/* Machine Counter Setup */
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#define CSR_MPHEVENT3 0x323
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#define CSR_MPHEVENT4 0x324
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#define CSR_MPHEVENT5 0x325
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#define CSR_MPHEVENT6 0x326
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#define CSR_MPHEVENT7 0x327
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#define CSR_MPHEVENT8 0x328
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#define CSR_MPHEVENT9 0x329
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#define CSR_MPHEVENT10 0x32a
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#define CSR_MPHEVENT11 0x32b
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#define CSR_MPHEVENT12 0x32c
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#define CSR_MPHEVENT13 0x32d
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#define CSR_MPHEVENT14 0x32e
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#define CSR_MPHEVENT15 0x32f
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#define CSR_MPHEVENT16 0x330
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#define CSR_MPHEVENT17 0x331
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#define CSR_MPHEVENT18 0x332
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#define CSR_MPHEVENT19 0x333
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#define CSR_MPHEVENT20 0x334
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#define CSR_MPHEVENT21 0x335
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#define CSR_MPHEVENT22 0x336
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#define CSR_MPHEVENT23 0x337
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#define CSR_MPHEVENT24 0x338
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#define CSR_MPHEVENT25 0x339
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#define CSR_MPHEVENT26 0x33a
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#define CSR_MPHEVENT27 0x33b
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#define CSR_MPHEVENT28 0x33c
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#define CSR_MPHEVENT29 0x33d
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#define CSR_MPHEVENT30 0x33e
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#define CSR_MPHEVENT31 0x33f
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/* Debug/Trace Registers */
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#define CSR_TSELECT 0x7a0
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA3 0x7a3
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/* Debug interface CSRs */
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#define CSR_DCSR 0x7b0
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#define CSR_DPC 0x7b1
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#define CSR_DSCRATCH 0x7b2
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/* In mstatus register */
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#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */
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#define MSTATUS_SIE (0x1 << 1) /* Supervisor Interrupt Enable */
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#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
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#define MSTATUS_SPIE (0x1 << 5) /* Supervisor Previous Interrupt Enable */
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#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
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#define MSTATUS_SPPU (0x0 << 8) /* Supervisor Previous Privilege (u-mode) */
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#define MSTATUS_SPPS (0x1 << 8) /* Supervisor Previous Privilege (s-mode) */
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#define MSTATUS_MPPU (0x0 << 11) /* Machine Previous Privilege (u-mode) */
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#define MSTATUS_MPPS (0x1 << 11) /* Machine Previous Privilege (s-mode) */
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#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
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#define MSTATUS_MPP_MASK (0x3 << 11)
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#define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */
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#define MSTATUS_FS_INIT (0x1 << 13)
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#define MSTATUS_FS_CLEAN (0x2 << 13)
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#define MSTATUS_FS_DIRTY (0x3 << 13)
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#define MSTATUS_MPRV (0x1 << 17) /* Modify Privilege */
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#define MSTATUS_SUM (0x1 << 18) /* S mode access to U mode memory */
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#define MSTATUS_MXR (0x1 << 19) /* Make executable / readable */
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#define MSTATUS_TVM (0x1 << 20) /* Trap access to satp from S mode */
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#define MSTATUS_TW (0x1 << 21) /* Trap WFI instruction from S mode */
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#define MSTATUS_TSR (0x1 << 22) /* Trap supervisor return (sret) */
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/* Mask of preserved bits for mstatus */
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#ifdef CONFIG_ARCH_RV32
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#define MSTATUS_WPRI (0xff << 23 | 0x15)
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#else
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#define MSTATUS_WPRI (UINT64_C(0x1ffffff) << 38 | UINT64_C(0x1ff) << 23 | 0x15)
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#endif
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/* In mie (machine interrupt enable) register */
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#define MIE_SSIE (0x1 << 1) /* Supervisor Software Interrupt Enable */
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#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
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#define MIE_STIE (0x1 << 5) /* Supervisor Timer Interrupt Enable */
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#define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */
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#define MIE_SEIE (0x1 << 9) /* Supervisor External Interrupt Enable */
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#define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */
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/* In mip (machine interrupt pending) register */
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#define MIP_SSIP (0x1 << 1)
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#define MIP_STIP (0x1 << 5)
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#define MIP_MTIP (0x1 << 7)
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#define MIP_SEIP (0x1 << 9)
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/* In sstatus register (which is a view of mstatus) */
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#define SSTATUS_SIE MSTATUS_SIE
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#define SSTATUS_SPIE MSTATUS_SPIE
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#define SSTATUS_SPPU MSTATUS_SPPU
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#define SSTATUS_SPPS MSTATUS_SPPS
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#define SSTATUS_FS MSTATUS_FS
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#define SSTATUS_FS_INIT MSTATUS_FS_INIT
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#define SSTATUS_FS_CLEAN MSTATUS_FS_CLEAN
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#define SSTATUS_FS_DIRTY MSTATUS_FS_DIRTY
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#define SSTATUS_SUM MSTATUS_SUM
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#define SSTATUS_MXR MSTATUS_MXR
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/* In sie register (which is a view of mie) */
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#define SIE_SSIE MIE_SSIE
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#define SIE_STIE MIE_STIE
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#define SIE_SEIE MIE_SEIE
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/* In sip register (which is a view of mip) */
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define SIP_SEIP MIP_SEIP
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/* In pmpcfg (PMP configuration) register */
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#define PMPCFG_R (1 << 0) /* readable ? */
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#define PMPCFG_W (1 << 1) /* writable ? */
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#define PMPCFG_X (1 << 2) /* executable ? */
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#define PMPCFG_RWX_MASK (7 << 0) /* access rights mask */
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#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
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#define PMPCFG_A_TOR (1 << 3) /* top of range */
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#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
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#define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */
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#define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */
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#define PMPCFG_L (1 << 7) /* locked ? */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_CSR_H */
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