chenwen@espressif.com e2a82f008a xtensa/esp32s3: Invalidate cache if the flash address used has a cache mapping. ... Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>		2023-11-29 03:57:50 -08:00
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include	esp32/irq: Allow IRAM ISRs to run during SPI flash operation	2023-11-10 09:11:35 +08:00
src	xtensa/esp32s3: Invalidate cache if the flash address used has a cache mapping.	2023-11-29 03:57:50 -08:00
Kconfig	xtensa/esp32s3: Add rtc heap support	2023-11-23 16:49:48 -08:00