9906163beb
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
imxrt:Kconfig fix formatting
imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map
imxrt:lpspi Fix build breakage from adding 1170
imxrt:Finish 1170 iomux and clockconfig versioning
imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4
imxrt:pmu remove duplicate dcd non 117x header
imxrt:lpspi Fix unused var warnings
imxrt:lpi2c Fix unused var warnings
imxrt:lowputs Fix unused var warnings
imxrt:imxrt117x_dmamux fix duplicate entries
imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them
imxrt:MPU Support the 1170
imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE
imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity
Author: Peter van der Perk <peter.vanderperk@nxp.com>
IMXRT7 Add LPUART 9/10/11/12 support
Author: David Sidrane <david.sidrane@nscdg.com>
imxrt:1170pinmux Add QTIMER pins
imxrt:1170pinmux Add GPT pins
imxrt:1170pinmux Add FLEXPWM pins
imxrt1170:pinmap Add GPIO_ENET_1G pinning
imxrt:enet Support ENET_1G
imxrt:periphclks rt1170 does not have canX_serial clock
imxrt:flexcan:Layer imxrt_ioctl
imxrt117x:memorymap added CAN3
imxrt:ADC support ver1 and ver2 for imxrt117x
imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn
imxrt:imxrt117x_ccm align CCM names with rt106x
imxrt:XBAR support larger number of selects needed on imxrt1170
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
FlexSPI AHB Region support, PIT rename for compatiblity
imxrt:USB Analog add VBUS_VALID_3V
FlexSPI expand prefetch registers for IMXRT117X
imxrt:Support Initialization of FlexRam without Running from OCRAM
imxrt: ocotp add UNIQUE_ID register definition
imxrt: enet use ocotp unique_id
imxrt: enet fixes for imxrt117x
imxrt: ethernet pinmux sion enable
imxrt:imxrt_periphclk_configure add memory sync
Flush the pipeline to prevent bus faults, by insuring a
peripheral is clocked before being accessed on return from
this function.
imxrt:Restructure gpioN to padmux mapping
imxrt:Add imxrt1170 daisy
imxrt: correct power modes for imxrt117x fixing hang on WFI
imxrt: imxrt117x TCM MPU config
imxrt: FlexRAM clocking DIV0 setup
imxrt: 117x periphclocks wait for status bit
imxrt: iomucx set pad settings correctly and allow reconfiguration
imxrt: enet align buffers 64-byte for optimal performance
Add DSC barriers for write-through cache support
imxrt: imxrt1170 use FlexCAN FD/ECC features
imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS
imxrt:Fix 1170 SNVS addressing
imxrt: enet set mii clock after ifdown so that phy keep working
nxstyle fixes
imxrt: preprocessor and include fixes
Fix configs
imxrt1170-evk clean defconfig
115 lines
4.8 KiB
C
115 lines
4.8 KiB
C
/****************************************************************************
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* arch/arm/include/imxrt/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
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/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
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* MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
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* MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
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* MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
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*/
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# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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/* but 4 doesn't exist */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1064DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1064CVL5A)
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/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz
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* MIMXRT1064CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1064DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1176DVMAA)
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/* MIMXRT1170DVMA TODO
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*/
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# define IMXRT_GPIO_NPORTS 13 /* Thirteen total ports */
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#else
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# error "Unknown i.MX RT chip type"
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds an 8-bit priority value, 0-15. The lower the
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* value, the greater the priority of the corresponding interrupt. The i.MX
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* RT processor implements only bits[7:4] of each field, bits[3:0] read as
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* zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
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