282 lines
10 KiB
C
282 lines
10 KiB
C
/************************************************************************************
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* configs/nucleo-l476rg/include/nucleo-l476rg.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIGS_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
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#define __CONFIGS_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However, as
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* shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG
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* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 80000000 Determined by PLL configuration
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* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz)
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* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 1 (STM32L4_PLLCFG_PLLM)
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* PLLN : 10 (STM32L4_PLLCFG_PLLN)
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* PLLP : 0 (STM32L4_PLLCFG_PLLP)
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* PLLQ : 0 (STM32L4_PLLCFG_PLLQ)
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* PLLR : 2 (STM32L4_PLLCFG_PLLR)
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* Flash Latency(WS) : 4
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* Prefetch Buffer : OFF
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* 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_LSE_FREQUENCY 32768
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#define STM32L4_BOARD_USEHSI 1
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/* REVISIT: Trimming of the HSI and MSI is not yet supported. */
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8
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* VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz
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* PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable
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* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable
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* PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* PLL output P is used for SAI
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* PLL output Q is used for OTG FS, SDMMC, RNG
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* PLL output R is used for SYSCLK
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* PLLP = 0 (not used)
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* PLLQ = 0 (not used)
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* PLLR = 2
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* PLLN = 10
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* PLLM = 1
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*
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* We will configure like this
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*
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* PLL source is HSI
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*
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* PLL_REF = STM32L4_HSI_FREQUENCY / PLLM
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* = 16,000,000 / 1
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* = 16,000,000
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*
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* PLL_VCO = PLL_REF * PLLN
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* = 16,000,000 * 10
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* = 160,000,000
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*
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* PLL_CLK = PLL_VCO / PLLR
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* = 160,000,000 / 2 = 80,000,000
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* PLL_48M1 = disabled
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* PLL_SAI3 = disabled
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*
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* ----------------------------------------
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*
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* PLLSAI1 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined
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*
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* SAI1VCO input frequency = PLL input clock frequency
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* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
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* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable
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* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable
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* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI1 disabled
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*
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* ----------------------------------------
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*
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* PLLSAI2 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined
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*
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* SAI2VCO input frequency = PLL input clock frequency
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* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
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* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable
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* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI2 disabled
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*
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* ----------------------------------------
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*
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* TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime.
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*
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* ----------------------------------------
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*
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* TODO These clock sources can be configured in Kconfig (this is not a board feature)
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* USART1
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* USART2
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* USART3
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* UART4
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* UART5
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* LPUART1
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* I2C1
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* I2C2
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* I2C3
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* LPTIM1
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* LPTIM2
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* SAI1
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* SAI2
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* CLK48
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* ADC
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* SWPMI
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* DFSDM
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*/
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32L4_PLLCFG_PLLR_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLM RCC_PLLSAI1CFG_PLLM(1)
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(10)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ 0
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#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR RCC_PLLSAI1CFG_PLLR(2)
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLM RCC_PLLSAI2CFG_PLLM(1)
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(10)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR RCC_PLLSAI2CFG_PLLR(2)
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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/* REVISIT : this can be configured */
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/* TODO SDMMC */
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIGS_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */
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