137 lines
4.7 KiB
C
137 lines
4.7 KiB
C
/****************************************************************************
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* arch/mips/src/mips32/up_irq.c
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*
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* Copyright (C) 2011, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/types.h>
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#include <arch/mips32/cp0.h>
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irq_save
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*
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* Description:
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* Save the current interrupt state and disable interrupts.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Interrupt state prior to disabling interrupts.
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*
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****************************************************************************/
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irqstate_t up_irq_save(void)
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{
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register irqstate_t status;
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register irqstate_t ret;
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status = cp0_getstatus(); /* Get CP0 status */
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ret = status; /* Save the status */
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status &= ~CP0_STATUS_INT_MASK; /* Clear all interrupt mask bits */
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status |= CP0_STATUS_INT_SW0; /* Enable only the SW0 interrupt */
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cp0_putstatus(status); /* Disable the rest of interrupts */
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return ret; /* Return saved status */
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}
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/****************************************************************************
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* Name: up_irq_restore
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*
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* Description:
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* Restore the previous up_irq_enable state (i.e., the one previously
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* returned by up_irq_save())
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*
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* Input Parameters:
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* state - The interrupt state to be restored.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void up_irq_restore(irqstate_t irqstate)
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{
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register irqstate_t status;
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status = cp0_getstatus(); /* Get CP0 status */
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status &= ~CP0_STATUS_INT_MASK; /* Clear all interrupt mask bits */
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irqstate &= CP0_STATUS_INT_MASK; /* Retain interrupt mask bits only */
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status |= irqstate; /* Set new interrupt mask bits */
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cp0_putstatus(status); /* Restore interrupt state */
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}
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/****************************************************************************
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* Name: up_irq_enable
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*
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* Description:
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* Enable interrupts
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*
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* Input Parameters:
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* None.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void up_irq_enable(void)
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{
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register irqstate_t status;
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/* Set the status register. It will be the same as the current status
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* register with some changes:
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*
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* 1. Clear the BEV bit (This bit should already be clear)
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* 2. Clear the UM bit so that the task executes in kernel mode
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* (This bit should already be clear)
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* 3. Clear all the Interrupt mask bits.
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* 4. Make sure the IE is set
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*/
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status = cp0_getstatus();
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status &= ~(CP0_STATUS_BEV | CP0_STATUS_UM);
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status &= ~CP0_STATUS_INT_MASK;
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status |= CP0_STATUS_IE;
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cp0_putstatus(status);
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}
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