Tiago Medicci Serrano 0ddb64555a esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation ... This commit provides an interface to register ISRs that run from IRAM and keeps track of the non-IRAM interrupts. It enables, for instance, to avoid disabling all the interrupts during a SPI flash operation: IRAM-enabled ISRs are, then, able to run during these operations.		2023-10-05 11:25:43 +08:00
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.gitignore
esp32s3_aliases.ld	xtensa/esp32s3: LCD controller driver	2023-09-19 11:38:05 +08:00
esp32s3_peripherals.ld
esp32s3_rom_aliases.ld	arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3	2023-08-14 16:29:21 -03:00
esp32s3_rom_api.ld	arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3	2023-08-14 16:29:21 -03:00
esp32s3_rom.ld	arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3	2023-08-14 16:29:21 -03:00
flat_memory.ld	arch/xtensa/esp32s3: Update MCUboot build process	2023-08-18 14:44:11 +08:00
kernel-space.ld
legacy_sections.ld	esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation	2023-10-05 11:25:43 +08:00
mcuboot_sections.ld
protected_memory.ld	arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3	2023-08-14 16:29:21 -03:00
user-space.ld