118 lines
4.9 KiB
Plaintext
118 lines
4.9 KiB
Plaintext
/****************************************************************************
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* boards/xtensa/esp32s3/common/scripts/protected_memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* ESP32-S3 Linker Script Memory Layout for Protected Mode
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* kernel-space.ld and user-space.ld contain output sections to link compiler
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* output into these memory blocks for the Kernel and User images,
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* respectively.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#include "esp32s3_aliases.ld"
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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/* The memory region starting from SRAM_IRAM_END up to 0x403dffff is
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* reserved to the 2nd stage bootloader for actually loading the NuttX
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* Application Image code and data into IRAM and DRAM. Otherwise the
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* Bootloader could end up overwriting itself and failing to load the NuttX
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* Application Image properly.
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*
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* For more information, refer to the bootloader linker scripts:
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* https://github.com/espressif/esp-idf/blob/dbb64db552068d440c2659294dcf2a5544fe3b6b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld#L52
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*/
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#define SRAM_IRAM_END 0x403cc700
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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#define SRAM_DRAM_START 0x3fc88000
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#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) /* 2nd stage bootloader iram_loader_seg start address */
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#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
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#define ICACHE_SIZE 0x8000
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
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#define DCACHE_SIZE 0x10000
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#ifdef CONFIG_ESP32S3_FLASH_4M
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# define FLASH_SIZE 0x400000
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#elif defined (CONFIG_ESP32S3_FLASH_8M)
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# define FLASH_SIZE 0x800000
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#elif defined (CONFIG_ESP32S3_FLASH_16M)
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# define FLASH_SIZE 0x1000000
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#endif
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MEMORY
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{
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metadata (RX) : org = 0x0, len = 0x30
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ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
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len = FLASH_SIZE - ORIGIN(ROM)
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/* Instruction RAM */
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UIRAM (RWX) : org = SRAM_IRAM_ORG, len = 16K
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KIRAM (RWX) : org = ORIGIN(UIRAM) + LENGTH(UIRAM), len = 32K
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/* Flash mapped instruction data. */
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/* The 0x20 offset for the KIROM region is a convenience for the Kernel
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* binary image generation in Espressif Application Image format.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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KIROM (RX) : org = 0x42000020, len = CONFIG_ESP32S3_KERNEL_IMAGE_SIZE - 0x20
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UIROM (RX) : org = ORIGIN(KIROM) + LENGTH(KIROM), len = FLASH_SIZE - LENGTH(KIROM)
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */
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KDRAM (RW) : org = ORIGIN(KIRAM) + LENGTH(KIRAM) - I_D_SRAM_OFFSET, len = CONFIG_ESP32S3_KERNEL_RAM_SIZE
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UDRAM (RW) : org = ORIGIN(KDRAM) + LENGTH(KDRAM), len = I_D_SRAM_SIZE - LENGTH(KDRAM)
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/* Flash mapped constant data */
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/* See KIROM region documentation above for the meaning of the 0x20 offset.
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*
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* The 0x30 offset for the UDROM region is a convenience for the User
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* binary image generation following a custom image format, which defines
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* a "metadata" output section containing some information that the Kernel
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* needs for properly configuring the External Flash MMU and initializing
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* SRAM contents when loading the User application image.
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*/
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KDROM (R) : org = 0x3c000020, len = CONFIG_ESP32S3_KERNEL_IMAGE_SIZE - 0x20
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UDROM (R) : org = ORIGIN(KDROM) + LENGTH(KDROM) + ORIGIN(ROM), len = FLASH_SIZE - LENGTH(KDROM) - ORIGIN(ROM)
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}
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