nuttx/arch/risc-v/include
Ville Juven b409d72e9d riscv/fpu: Restore correct lazy-FPU functionality
- Save the FPU registers into the tcb so they don't get lost if the stack
  frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
  - Save ONLY if FPU is dirty
  - Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
2023-07-31 07:48:53 -07:00
..
bl602
c906
esp32c3
esp32c6
espressif arch/risc-v/espressif: Add full GPIO support 2023-06-24 13:11:45 +08:00
fe310
hpm6750
k210
litex litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
mpfs
qemu-rv
rv32m1
.gitignore
arch.h risc-v: SV32 MMU support for qemu-rv. 2023-03-29 22:15:19 +09:00
barriers.h riscv/barrier: Define more granular memory barriers 2023-06-14 16:14:57 -03:00
csr.h
elf.h
inttypes.h
irq.h riscv/fpu: Restore correct lazy-FPU functionality 2023-07-31 07:48:53 -07:00
limits.h
mode.h
setjmp.h
spinlock.h
stdarg.h
syscall.h arch/risc-v: change up_saveusercontext to assembly code 2023-04-27 17:34:30 +08:00
types.h