151 lines
5.3 KiB
C
151 lines
5.3 KiB
C
/************************************************************************************
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* configs/mikroe_stm32f4/src/up_clockconfig.c
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "mikroe-stm32f4-internal.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_board_clockconfig
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*
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* Description:
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* The Mikroe-STM32F4 board does not have an external crystal, so it must rely
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* on the internal 16Mhz RC oscillator. The default clock configuration in the
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* OS for the STM32 architecture assumes an external crystal, so we must provide
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* a board specific clock configuration routine.
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*
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************************************************************************************/
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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void stm32_board_clockconfig(void)
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{
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uint32_t regval;
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/* Configure chip clocking to use the internal 16Mhz RC oscillator.
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*
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* NOTE: We will assume the HSIRDY (High Speed Internal RC Ready) bit is
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* set, otherwise we wouldn't be here executing code.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32_RCC_APB1ENR);
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regval = getreg32(STM32_PWR_CR);
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regval |= PWR_CR_VOS;
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putreg32(regval, STM32_PWR_CR);
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/* Set the HCLK source/divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PLL dividers and multipliers to configure the main PLL */
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regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
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RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
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putreg32(regval, STM32_RCC_PLLCFG);
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/* Enable the main PLL */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the PLL is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
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;
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/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
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#else
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
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#endif
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putreg32(regval, STM32_FLASH_ACR);
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/* Select the main PLL as system clock source */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_PLL;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until the PLL source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
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;
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}
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#endif
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