270aa2848a
BCM2708: Add enough infrastructrue (more stubs) to get a clean compilation of the Pi Zero configuration (with many undefined things at link time).
BCM2708: Add basic interrupt handling logic
BCM2708: Add interrupt register definitions.
BCM2708: Add irq.h header file
BCM2708/Pi zero: bcm_boot.c and bcm_memorymap.h now compile. Added pizero linker script.
BCM2708/Pi Zero: Add Make.defs needed to build.
arch/arm/include/bcm2708, arch/arm/src/bcm2708, configs/pizero: Add some basic build and configuration logic.
configs/pizero: Add some basic structure of the Rasperry Pi Zero port.
Created directory configs/pizero. Nothing there now but a README.txt file.
Add initial boot.c and memorymap.c files
Author: Alan Carvalho de Assis <acassis@gmail.com>
Add AUX/UART/SPI registers definition
Author: Alan Carvalho de Assis <acassis@gmail.com>
Pizero GPIO registers
* Initial commit to add GPIO definitions
* Add remaining GPIO registers definition
Alan Carvalho de Assis <acassis@gmail.com>
BCM2708 memory map: Add VBASE defintions; fix VCSDRAM address per Alan; move all virtual address to the bottom of the file to avoid confusion -- top is all physical address; bottom is all veritural address.
Add initial memory map to BCM2708/BCM2835
Alan Carvalho de Assis <acassis@gmail.com>
175 lines
7.8 KiB
C
175 lines
7.8 KiB
C
/****************************************************************************
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* arch/arm/include/bcm2708/irq.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_BCM2708_IRQ_H
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#define __ARCH_ARM_INCLUDE_BCM2708_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/bcm2708/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Chip-Specific External interrupts */
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#if defined(CONFIG_ARCH_CHIP_BCM2835)
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/* Interrupt decode algorithm:
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*
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* 1) Check bits 0 through BPR_BIT_LAST in the basic pending register. For
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* each bit set, dispatch IRQ = bit number
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* 2) If bits set in pending register 1, check bits IPR1_BIT_FIRST through
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* IPR1_BIT_LAST for the pending 1 register. For each bit set, dispatch
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* IRQ = bit number + IPR1_IRQ_FIRST - IPR1_BIT_FIRST.
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* 2) If bits set in pending register 2, check bits IPR2_BIT_FIRST through
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* IPR2_BIT_LAST for the pending 2 register. For each bit set, dispatch
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* IRQ = bit number + IPR2_IRQ_FIRST - IPR2_BIT_FIRST.
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*/
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/* Basic pending register */
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#define BPR_IRQ_FIRST 0 /* IRQ of first defined bit */
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#define BPR_BIT_FIRST 0 /* First defined bit */
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#define BCM_IRQ_ARM_TIMER 0 /* Bit 0: ARM Timer IRQ pending */
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#define BCM_IRQ_ARM_MAILBOX 1 /* Bit 1: ARM Mailbox IRQ pending */
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#define BCM_IRQ_ARM_DOORBELL_0 2 /* Bit 2: ARM Doorbell 0 IRQ pending */
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#define BCM_IRQ_ARM_DOORBELL_1 3 /* Bit 3: ARM Doorbell 2 IRQ pending */
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#define BCM_IRQ_GPU0_HALTED 4 /* Bit 4: GPU0 halted IRQ pending
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* (Or GPU1 halted if bit 10 of control
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* register 1 is set) */
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#define BCM_IRQ_GPU1_HALTED 5 /* Bit 5: GPU1 halted IRQ pending */
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#define BCM_IRQ_ILLEGAL_ACCESS_1 6 /* Bit 6: Illegal access type 1 IRQ pending */
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#define BCM_IRQ_ILLEGAL_ACCESS_0 7 /* Bit 7: Illegal access type 0 IRQ pending */
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#define BCM_BIT_PENDING_1 8 /* Bit 8: Bits set in pending register 1 */
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#define BCM_BIT_PENDING_2 9 /* Bit 9: Bits set in pending register 2 */
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#define BCM_IRQ_GPU_IRQ_7 10 /* Bit 10: GPU IRQ 7 */
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#define BCM_IRQ_GPU_IRQ_9 11 /* Bit 10: GPU IRQ 9 */
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#define BCM_IRQ_GPU_IRQ_10 12 /* Bit 10: GPU IRQ 10 */
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#define BCM_IRQ_GPU_IRQ_18 13 /* Bit 10: GPU IRQ 18 */
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#define BCM_IRQ_GPU_IRQ_19 14 /* Bit 10: GPU IRQ 19 */
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#define BCM_IRQ_GPU_IRQ_53 15 /* Bit 10: GPU IRQ 53 */
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#define BCM_IRQ_GPU_IRQ_54 16 /* Bit 10: GPU IRQ 54 */
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#define BCM_IRQ_GPU_IRQ_55 17 /* Bit 10: GPU IRQ 55 */
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#define BCM_IRQ_GPU_IRQ_56 18 /* Bit 10: GPU IRQ 56 */
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#define BCM_IRQ_GPU_IRQ_57 19 /* Bit 10: GPU IRQ 57 */
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#define BCM_IRQ_GPU_IRQ_62 20 /* Bit 10: GPU IRQ 61 */
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#define BPR_BIT_IRQMASK 0x001ffcff /* Mask of defined interrupts */
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#define BPR_BIT_LAST 20 /* IRQ of last defined bit */
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#define BPR_IRQ_LAST 20 /* Last defined bit */
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/* IRQ pending 1 register */
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#define IPR1_IRQ_FIRST (BPR_IRQ_LAST + 1) /* IRQ of first defined bit */
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#define IPR1_BIT_FIRST (29) /* First defined bit */
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#define BCM_IRQ_AUX_INT IPR1_IRQ_FIRST /* Bit 29: Aux interrupt */
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#define IPR1_BIT_IRQMASK 0x20000000 /* Mask of defined interrupts */
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#define IPR1_IRQ_LAST BCM_IRQ_AUX_INT /* IRQ of last defined bit */
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#define IPR1_BIT_LAST (29) /* Last defined bit */
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/* IRQ pending 1 register */
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#define IPR2_IRQ_FIRST (IPR1_IRQ_LAST + 1) /* IRQ of first defined bit */
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#define IPR2_BIT_FIRST (11) /* First defined bit */
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#define BCM_IRQ_I2C_SPI_SLV (IPR2_IRQ_FIRST + 11) /* Bit 11: 43 I2C/SPI slave */
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#define BCM_IRQ_PWA0 (IPR2_IRQ_FIRST + 13) /* Bit 12: 45 PWA0 */
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#define BCM_IRQ_PWA1 (IPR2_IRQ_FIRST + 14) /* Bit 14: 46 PWA1 */
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#define BCM_IRQ_SMI (IPR2_IRQ_FIRST + 16) /* Bit 16: 48 SMI */
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#define BCM_IRQ_GPIO0 (IPR2_IRQ_FIRST + 17) /* Bit 17: 49 GPIO interrupt 0 */
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#define BCM_IRQ_GPIO1 (IPR2_IRQ_FIRST + 18) /* Bit 18: 50 GPIO interrupt 1 */
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#define BCM_IRQ_GPIO2 (IPR2_IRQ_FIRST + 19) /* Bit 19: 51 GPIO interrupt 2 */
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#define BCM_IRQ_GPIO3 (IPR2_IRQ_FIRST + 20) /* Bit 20: 52 GPIO interrupt 3 */
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#define BCM_IRQ_I2C (IPR2_IRQ_FIRST + 21) /* Bit 21: 53 I2C interrupt */
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#define BCM_IRQ_SPI (IPR2_IRQ_FIRST + 22) /* Bit 22: 54 SPI interrupt */
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#define BCM_IRQ_PCM (IPR2_IRQ_FIRST + 23) /* Bit 23: 55 PCM interrupt */
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#define BCM_IRQ_UART (IPR2_IRQ_FIRST + 24) /* Bit 24: 57 UART interrupt */
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#define IPR2_BIT_IRQMASK 0x01ff6800 /* Mask of defined interrupts */
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#define IPR2_IRQ_LAST BCM_IRQ_UART /* IRQ of last defined bit */
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#define IPR2_BIT_LAST (24) /* Last defined bit */
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/* Number of interrupts */
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#define NR_IRQS (IPR2_IRQ_LAST + 1)
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#else
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# error Unrecognized BCM2708 chip
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_BCM2708_IRQ_H */
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