304 lines
10 KiB
C
304 lines
10 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm32f334-disco/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* HSI - Internal 8 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - 8 MHz from MCO output of ST-LINK
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL source is HSE/1, PLL multipler is 9:
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* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
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*/
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */
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/* Timers driven from APB2 will be PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY
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/* LED definitions **********************************************************/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_LED4 3
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#define BOARD_NLEDS 4
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on
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* board the stm32f334-disco. The following definitions describe how NuttX
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* controls the LEDs:
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*/
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#define LED_STARTED 0 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */
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#define LED_STACKCREATED 3 /* LED3 */
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#define LED_INIRQ 4 /* LED1 + LED3 */
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#define LED_SIGNAL 5 /* LED2 + LED3 */
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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/* Button definitions *******************************************************/
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/* The STM32F334-DISCO supports two buttons; only one button is controllable
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* by software:
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*
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* B1 USER: user button connected to the I/O PA0 of the STM32F334R8.
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* B2 RESET: push button connected to NRST is used to RESET the
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* STM32F334R8.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN_RX_2
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#define GPIO_CAN1_TX GPIO_CAN_TX_2
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/* I2C */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3
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/* SPI */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* TIM */
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#define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_2
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#define GPIO_TIM2_CH3OUT GPIO_TIM2_CH3OUT_3
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#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2
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#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_4
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#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_2
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/* USART */
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#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */
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#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */
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/* Board configuration for powerled example:
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* - Set HRTIM TIMC output 1 (PB12) on PERIOD.
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* - Reset HRTIM TIMC output 1 on HRTIM EEV2.
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* - HRTIM EEV2 is connected to COMP4 output which works as current limit.
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* - COMP4 inverting input is connected to DAC1CH1 output.
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* - COMP4 non-inverting input (PB1) is connceted to current sense
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* resitor (1 Ohm).
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* - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used
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* to provide slope compensation.
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*/
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#if defined(CONFIG_EXAMPLES_POWERLED)
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/* Comparators configuration ************************************************/
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#define COMP4_INM COMP_INMSEL_DAC1CH1
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/* HRTIM configuration ******************************************************/
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#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1
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#define HRTIM_TIMC_MODE HRTIM_MODE_CONT
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#define HRTIM_TIMC_DMA (HRTIM_DMA_REP|HRTIM_DMA_CMP1|HRTIM_DMA_CMP2| \
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HRTIM_DMA_CMP3|HRTIM_DMA_CMP4)
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#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER
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#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_EXTEVNT2
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#define HRTIM_TIMC_CH1_IDLE_STATE HRTIM_IDLE_INACTIVE
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#define HRTIM_EEV_SAMPLING HRTIM_EEV_SAMPLING_d1
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#define HRTIM_EEV2_SRC HRTIM_EEV_SRC_ANALOG
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#define HRTIM_EEV2_FILTER HRTIM_EEV_DISABLE
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#define HRTIM_EEV2_POL HRTIM_EEV_POL_HIGH
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#define HRTIM_EEV2_SEN HRTIM_EEV_SEN_LEVEL
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#define HRTIM_EEV2_MODE HRTIM_EEV_MODE_FAST
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#define HRTIM_BURST_CLOCK HRTIM_BURST_CLOCK_HRTIM
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#define HRTIM_BURST_PRESCALER HRTIM_BURST_PRESCALER_1
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#define HRTIM_BURST_TRIGGERS 0
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/* DMA channels *************************************************************/
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/* DAC */
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#define DAC1CH1_DMA_CHAN DMACHAN_HRTIM1_C
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#endif /* CONFIG_EXAMPLES_POWERLED */
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/* Board configuration for SMPS example:
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* PA8 - HRTIM_CHA1
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* PA9 - HRTIM_CHA2
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* PA10 - HRTIM_CHB1
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* PA11 - HRTIM_CHB2
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* VIN - ADC Channel 2 (PA1)
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* VOUT - ADC Channel 4 (PA3)
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*/
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#if defined(CONFIG_EXAMPLES_SMPS)
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/* HRTIM configuration ******************************************************/
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/* Timer A configuration - Buck operations */
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#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_1
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#define HRTIM_TIMA_MODE HRTIM_MODE_CONT
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#define HRTIM_TIMA_UPDATE 0
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#define HRTIM_TIMA_RESET 0
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#define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_NONE
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#define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_NONE
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#define HRTIM_TIMA_CH2_SET HRTIM_OUT_SET_NONE
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#define HRTIM_TIMA_CH2_RST HRTIM_OUT_RST_NONE
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#define HRTIM_TIMA_DT_FSLOCK HRTIM_DT_LOCK
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#define HRTIM_TIMA_DT_RSLOCK HRTIM_DT_LOCK
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#define HRTIM_TIMA_DT_FVLOCK HRTIM_DT_RW
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#define HRTIM_TIMA_DT_RVLOCK HRTIM_DT_RW
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#define HRTIM_TIMA_DT_FSIGN HRTIM_DT_SIGN_POSITIVE
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#define HRTIM_TIMA_DT_RSIGN HRTIM_DT_SIGN_POSITIVE
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#define HRTIM_TIMA_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1
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/* Timer B configuration - Boost operations */
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#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_1
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#define HRTIM_TIMB_MODE HRTIM_MODE_CONT
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#define HRTIM_TIMB_UPDATE 0
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#define HRTIM_TIMB_RESET 0
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#define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_NONE
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#define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_NONE
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#define HRTIM_TIMB_CH2_SET HRTIM_OUT_SET_NONE
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#define HRTIM_TIMB_CH2_RST HRTIM_OUT_RST_NONE
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#define HRTIM_TIMB_DT_FSLOCK HRTIM_DT_LOCK
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#define HRTIM_TIMB_DT_RSLOCK HRTIM_DT_LOCK
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#define HRTIM_TIMB_DT_FVLOCK HRTIM_DT_RW
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#define HRTIM_TIMB_DT_RVLOCK HRTIM_DT_RW
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#define HRTIM_TIMB_DT_FSIGN HRTIM_DT_SIGN_POSITIVE
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#define HRTIM_TIMB_DT_RSIGN HRTIM_DT_SIGN_POSITIVE
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#define HRTIM_TIMB_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1
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#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4
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/* DMA channels *************************************************************/
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#endif /* CONFIG_EXAMPLES_SMPS */
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#endif /* __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H */
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