56 lines
2.3 KiB
C
56 lines
2.3 KiB
C
/****************************************************************************
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* arch/risc-v/include/nr5m100/irq.h
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* include/arch/nr5m100/irq.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
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#define __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#if defined(CONFIG_NR5_NR5M1XX)
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# include <arch/chip/nr5m1xx_irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NR5_IRQ_TRAP 0
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#define EPIC_STATUS_PRI_MASK 0x001C
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#define EPIC_STATUS_INT_PRI_MASK 0x01C0
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#define EPIC_STATUS_INT_PRI1 0x0040
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#endif /* __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H */
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