Manohara HK b154531838 I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S. ... The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor. But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's. It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition) So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.		2017-02-13 06:33:15 -06:00
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include	Costmetic changes from review of last PR.	2017-02-09 08:39:31 -10:00
src	I found an issue inside the cp15_coherent_dcache function in file, arch/arm/src/armv7-r/cp15_coherent_dcache.S.	2017-02-13 06:33:15 -06:00
Kconfig	Merged in david_s5/nuttx/upstream_2_greg_f7_config (pull request #199)	2017-01-23 23:08:50 +00:00