1250 lines
38 KiB
C
1250 lines
38 KiB
C
/****************************************************************************
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* arch/avr/src/sam34/sam4l_clockconfig.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/sam4l_pm.h"
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#include "chip/sam4l_scif.h"
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#include "chip/sam4l_bpm.h"
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#include "chip/sam4l_bscif.h"
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#include "chip/sam4l_flashcalw.h"
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#include "sam_periphclks.h"
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#include "sam_clockconfig.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_ARCH_RAMFUNCS
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# error "CONFIG_ARCH_RAMFUNCS must be defined"
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#endif
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/* Nominal frequencies in on-chip RC oscillators. These may frequencies
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* may vary with temperature changes.
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*/
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#define SAM_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */
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#define SAM_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */
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#define SAM_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */
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#define SAM_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */
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#define SAM_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */
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#define SAM_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
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#define SAM_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
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/* Oscillator 0. This might be the system clock or the source clock for
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* either PLL0 or DFPLL. It might also be needed if OSC0 is the source
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* clock for GCLK9.
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*
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* By selecting CONFIG_SAM34_OSC0, you can also force the clock to be enabled
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* at boot time.
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*/
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#if defined(CONFIG_SAM34_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \
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defined(BOARD_DFLL0_SOURCE_OSC0) || defined(BOARD_PLL0_SOURCE_OSC0) || \
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defined(BOARD_GLCK9_SOURCE_OSC0)
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# define NEED_OSC0 1
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#endif
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#ifdef NEED_OSC0
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# if !defined(BOARD_OSC0_STARTUP_US)
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# error BOARD_OSC0_STARTUP_US is not defined
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# elif BOARD_OSC0_STARTUP_US == 0
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_0
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# define SAM_OSC0_STARTUP_TIMEOUT 8
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# elif BOARD_OSC0_STARTUP_US <= 557
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_64
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# define SAM_OSC0_STARTUP_TIMEOUT 80
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# elif BOARD_OSC0_STARTUP_US <= 1100
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_128
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# define SAM_OSC0_STARTUP_TIMEOUT 160
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# elif BOARD_OSC0_STARTUP_US <= 18000
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_2K
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# define SAM_OSC0_STARTUP_TIMEOUT 2560
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# elif BOARD_OSC0_STARTUP_US <= 36000
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_4K
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# define SAM_OSC0_STARTUP_TIMEOUT 5120
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# elif BOARD_OSC0_STARTUP_US <= 71000
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_8K
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# define SAM_OSC0_STARTUP_TIMEOUT 10240
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# elif BOARD_OSC0_STARTUP_US <= 143000
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_16K
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# define SAM_OSC0_STARTUP_TIMEOUT 20480
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# elif BOARD_OSC0_STARTUP_US <= 285000
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# define SAM_OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_32K
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# define SAM_OSC0_STARTUP_TIMEOUT 40960
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# else
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# error BOARD_OSC0_STARTUP_US is out of range
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# endif
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# ifdef BOARD_OSC0_IS_XTAL
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# define SAM_OSC0_MODE_VALUE SCIF_OSCCTRL0_MODE
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# if BOARD_OSC0_FREQUENCY < 2000000
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# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(0)
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# elif BOARD_OSC0_FREQUENCY < 4000000
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# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(1)
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# elif BOARD_OSC0_FREQUENCY < 8000000
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# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(2)
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# elif BOARD_OSC0_FREQUENCY < 16000000
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# define SAM_OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(3)
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# else
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# define SAM_OSC0_GAIN_VALUE ((0x1u << 4) | SCIF_OSCCTRL0_GAIN(0))
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# endif
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# else
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# define SAM_OSC0_MODE_VALUE 0
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# define SAM_OSC0_GAIN_VALUE 0
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# endif
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#endif
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/* OSC32. The 32K oscillator may be the source clock for DFPLL0 or
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* the source clock for GLK9 that might be used to driver PLL0.
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*
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* By selecting CONFIG_SAM34_OSC32K, you can also force the clock to be
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* enabled at boot time. OSC32 may needed by other devices as well
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* (AST, WDT, PICUART, RTC).
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*/
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#if defined(CONFIG_SAM34_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K) || \
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defined(BOARD_GLCK9_SOURCE_OSC32K)
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# define NEED_OSC32K 1
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#endif
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#ifdef NEED_OSC32K
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# if !defined(BOARD_OSC32_STARTUP_US)
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# error BOARD_OSC32_STARTUP_US is not defined
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# elif BOARD_OSC32_STARTUP_US == 0
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_0
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# elif BOARD_OSC32_STARTUP_US <= 1100
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128
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# elif BOARD_OSC32_STARTUP_US <= 72300
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_8K
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# elif BOARD_OSC32_STARTUP_US <= 143000
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_16K
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# elif BOARD_OSC32_STARTUP_US <= 570000
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_64K
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# elif BOARD_OSC32_STARTUP_US <= 1100000
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_128K
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# elif BOARD_OSC32_STARTUP_US <= 2300000
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_256K
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# elif BOARD_OSC32_STARTUP_US <= 4600000
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# define SAM_OSC32_STARTUP_VALUE BSCIF_OSCCTRL32_STARTUP_512K
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# else
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# error BOARD_OSC32_STARTUP_US is out of range
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# endif
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# ifdef BOARD_OSC32_IS_XTAL
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# define SAM_OSC32_MODE_VALUE SCIF_OSCCTRL32_MODE_XTAL
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# else
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# define SAM_OSC32_MODE_VALUE BSCIF_OSCCTRL32_MODE_EXTCLK
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# endif
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# ifndef BOARD_OSC32_SELCURR
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# define BOARD_OSC32_SELCURR BSCIF_OSCCTRL32_SELCURR_300
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# endif
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#endif
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/* RC80M. This might be the system clock or the source clock for the DFPLL
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* or it could be the source for GCLK9 that drives PLL0.
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*
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* By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled
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* at boot time.
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*/
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#if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \
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defined(BOARD_DFLL0_SOURCE_RC80M) || BOARD_GLCK9_SOURCE_RC80M
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# define NEED_RC80M 1
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#endif
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/* RCFAST. The 12/8/4 fast RC oscillator may be used as the system clock
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* or as the source for GLCK9 that drives PLL0.
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* If not then, it may be enabled by setting the CONFIG_SAM34_RCFASTxM
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* configuration variable.
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*/
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#if defined(CONFIG_SAM34_RCFAST12M)
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# undef CONFIG_SAM34_RCFAST8M
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# undef CONFIG_SAM34_RCFAST4M
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#elif defined(CONFIG_SAM34_RCFAST8M)
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# undef CONFIG_SAM34_RCFAST4M
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#endif
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#if defined(BOARD_SYSCLK_SOURCE_FCFAST12M)
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# if defined(CONFIG_SAM34_RCFAST8M) || defined(CONFIG_SAM34_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST12M inconsistent with CONFIG_SAM34_RCFAST8/4M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY
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#elif defined(BOARD_SYSCLK_SOURCE_FCFAST8M)
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# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST8M inconsistent with CONFIG_SAM34_RCFAST12/4M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY
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#elif defined(BOARD_SYSCLK_SOURCE_FCFAST4M)
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# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST8M)
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# error BOARD_SYSCLK_SOURCE_FCFAST4M inconsistent with CONFIG_SAM34_RCFAST12/8M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY
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#elif defined(CONFIG_SAM34_RCFAST12M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY
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#elif defined(CONFIG_SAM34_RCFAST8M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY
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#elif defined(CONFIG_SAM34_RCFAST4M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY
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#endif
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/* RC1M. The 1M RC oscillator may be used as the system block or
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* may be the source clock for GLCK9 that drives PLL0
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*
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* By selecting CONFIG_SAM34_RC1M, you can also force the clock to be
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* enabled at boot time.
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*/
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#if defined(CONFIG_SAM34_RC1M) || defined(BOARD_SYSCLK_SOURCE_RC1M) || \
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defined(BOARD_GLCK9_SOURCE_RC1M)
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# define NEED_RC1M 1
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#endif
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/* RC32K. The 32KHz RC oscillator may be used as the input to DFLL0
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* or as the input to GCLK9 that drives PLL0.
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*
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* By selecting CONFIG_SAM34_RC32K, you can also force the clock to be
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* enabled at boot time.
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*/
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#if defined(CONFIG_SAM34_RC32K) || defined(BOARD_DFLL0_SOURCE_RC32K) || \
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defined(BOARD_GLCK9_SOURCE_RC32K)
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# define NEED_RC32K 1
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#endif
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/* GCLK9. May used as a source clock for PLL0 */
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#ifdef BOARD_PLL0_SOURCE_GCLK9
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# define NEED_GLCK9 1
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#ifdef NEED_GLCK9
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# if defined(BOARD_GLCK9_SOURCE_RCSYS)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RCSYS
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# define SAM_GCLK9_FREQUENCY SAM_RCSYS_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_OSC32K)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC32K
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# define SAM_GCLK9_FREQUENCY BOARD_OSC32_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_DFLL0)
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# error BOARD_GLCK9_SOURCE_DFLL0 is not supported
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# elif defined(BOARD_GLCK9_SOURCE_OSC0)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_OSC0
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# define SAM_GCLK9_FREQUENCY BOARD_OSC0_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_RC80M)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC80M
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# define SAM_GCLK9_FREQUENCY SAM_RC80M_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_RCFAST)
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# error BOARD_GLCK9_SOURCE_RCFAST is not supported (needs RCFAST configuration)
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# elif defined(BOARD_GLCK9_SOURCE_RC1M)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC1M
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# define SAM_GCLK9_FREQUENCY SAM_RCFAST_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_CPUCLK)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_CPUCLK
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# define SAM_GCLK9_FREQUENCY BOARD_CPU_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_HSBCLK)
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# error BOARD_GLCK9_SOURCE_HSBCLK is not supported (REVISIT)
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# elif defined(BOARD_GLCK9_SOURCE_PBACLK)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBACLK
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# define SAM_GCLK9_FREQUENCY BOARD_PBA_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_PBBCLK)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBBCLK
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# define SAM_GCLK9_FREQUENCY BOARD_PBB_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_PBCCLK)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBCCLK
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# define SAM_GCLK9_FREQUENCY BOARD_PBC_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_PBDCLK)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_PBDCLK
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# define SAM_GCLK9_FREQUENCY BOARD_PBD_FREQUENCY
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# elif defined(BOARD_GLCK9_SOURCE_RC32K)
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# define SAM_GCLK9_SOURCE_VALUE SCIF_GCCTRL_OSCSEL_RC32K
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# define SAM_GCLK9_FREQUENCY SAM_RC32K_FREQUENCY
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# else
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# error Missing GCLK9 source
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# endif
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#endif
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/* PLL0 */
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#ifdef BOARD_SYSCLK_SOURCE_PLL0
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/* PLL0 source */
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# if defined(BOARD_PLL0_SOURCE_OSC0)
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# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_OSC0
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# define SAM_PLL0_SOURCE_FREQUENCY BOARD_OSC0_FREQUENCY
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# elif defined(BOARD_PLL0_SOURCE_GCLK9)
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# define SAM_PLL0_SOURCE SCIF_PLL0_PLLOSC_GCLK9
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# define SAM_PLL0_SOURCE_FREQUENCY SAM_GCLK9_FREQUENCY
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# else
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# error Missing PLL0 source
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# endif
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/* PLL0 Multipler and Divider */
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# if !defined(BOARD_PLL0_MUL)
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# error BOARD_PLL0_MUL is not defined
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# elif BOARD_PLL0_MUL <= 2 || BOARD_PLL0_MUL > 16
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# error BOARD_PLL0_MUL is out of range
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# endif
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# if !defined(BOARD_PLL0_DIV)
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# error BOARD_PLL0_DIV is not defined
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# elif BOARD_PLL0_DIV < 1 || BOARD_PLL0_DIV > 15
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# error BOARD_PLL0_DIV is out of range
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# endif
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/* PLL0 frequency ranges */
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# define SAM_PLL0_MIN_FREQUENCY 40000000
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# define SAM_PLL0_MAX_FREQUENCY 240000000
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/* PLL0 VCO frequency */
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# define SAM_PLL0_VCO_DIV1_FREQUENCY \
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(SAM_PLL0_SOURCE_FREQUENCY * BOARD_PLL0_MUL / BOARD_PLL0_DIV)
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# if (SAM_PLL0_VCO_DIV1_FREQUENCY < SAM_PLL0_MIN_FREQUENCY) || \
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(SAM_PLL0_VCO_DIV1_FREQUENCY > SAM_PLL0_MAX_FREQUENCY)
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# error PLL0 VCO frequency is out of range
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# endif
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/* PLL0 Options:
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*
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* PLL0 supports an option to divide the frequency output by 2. We
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* will do this division to bring the internal VCO frequency up to the
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* minimum value
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*
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* PLL0 operates in two frequency ranges as determined by
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* SCIF_PLL0_PLLOPT_FVO:
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*
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* 0: 80MHz < fvco < 180MHz
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* 1: 160MHz < fvco < 240MHz
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*
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* Select the correct frequncy range using the recommended threshold
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* value.
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*/
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# if SAM_PLL0_VCO_DIV1_FREQUENCY < (2*SAM_PLL0_MIN_FREQUENCY) && BOARD_PLL0_MUL <= 8
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# define SAM_PLL0_VCO_FREQUENCY (2 * SAM_PLL0_VCO_DIV1_FREQUENCY)
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# define SAM_PLL0_MUL (2 * BOARD_PLL0_MUL)
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# if SAM_PLL0_VCO_FREQUENCY > (SAM_PLL0_VCO_RANGE_THRESHOLD / 2)
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|
# define SAM_PLL0_OPTIONS (SCIF_PLL0_PLLOPT_DIV2 | SCIF_PLL0_PLLOPT_FVO)
|
|
# else
|
|
# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_DIV2
|
|
# endif
|
|
|
|
# else
|
|
# define SAM_PLL0_VCO_FREQUENCY SAM_PLL0_VCO_DIV1_FREQUENCY
|
|
# define SAM_PLL0_MUL BOARD_PLL0_MUL
|
|
|
|
# if SAM_PLL0_VCO_FREQUENCY > SAM_PLL0_VCO_RANGE_THRESHOLD
|
|
# define SAM_PLL0_OPTIONS SCIF_PLL0_PLLOPT_FVO
|
|
# else
|
|
# define SAM_PLL0_OPTIONS 0
|
|
# endif
|
|
# endif
|
|
|
|
/* DPLL0 reference clock */
|
|
|
|
# if defined(BOARD_DFLL0_SOURCE_RCSYS)
|
|
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS
|
|
# elif defined(BOARD_DFLL0_SOURCE_OSC32K)
|
|
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC32K
|
|
# elif define(BOARD_DFLL0_SOURCE_OSC0)
|
|
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_OSC0
|
|
# elif define(BOARD_DFLL0_SOURCE_RC80M)
|
|
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC80M
|
|
# elif define(BOARD_DFLL0_SOURCE_RC32K)
|
|
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RC32K
|
|
# else
|
|
# error No DFLL0 source for reference clock defined
|
|
# endif
|
|
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Private Types
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Private Function Prototypes
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Global Variables
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Private Variables
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Private Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: sam_picocache
|
|
*
|
|
* Description:
|
|
* Initialiaze the PICOCACHE.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_SAM34_PICOCACHE
|
|
static inline void sam_picocache(void)
|
|
{
|
|
/* Enable clocking to the PICOCACHE */
|
|
|
|
sam_hsb_enableperipheral(PM_HSBMASK_HRAMC1);
|
|
sam_pbb_enableperipheral(PM_PBBMASK_HRAMC1);
|
|
|
|
/* Enable the PICOCACHE and wait for it to become ready */
|
|
|
|
putreg32(PICOCACHE_CTRL_CEN, SAM_PICOCACHE_CTRL);
|
|
while ((getreg32(SAM_PICOCACHE_SR) & PICOCACHE_SR_CSTS) == 0);
|
|
}
|
|
#else
|
|
# define sam_picocache()
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enableosc0
|
|
*
|
|
* Description:
|
|
* Initialiaze OSC0 settings per the definitions in the board.h file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_OSC0
|
|
static inline void sam_enableosc0(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Enable and configure OSC0 */
|
|
|
|
regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | SAM_OSC0_MODE_VALUE |
|
|
SCIF_OSCCTRL0_OSCEN;
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(regval, SAM_SCIF_OSCCTRL0);
|
|
|
|
/* Wait for OSC0 to be ready */
|
|
|
|
while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enableosc32
|
|
*
|
|
* Description:
|
|
* Initialiaze the 32KHz oscillator per settings in the board.h header
|
|
* file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_OSC32K
|
|
static inline void sam_enableosc32(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Set up the OSCCTRL32 register using settings from the board.h file.
|
|
* Also enable the oscillator and provide bother the 32KHz and 1KHz output.
|
|
*/
|
|
|
|
regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | SAM_OSC32_MODE_VALUE |
|
|
BSCIF_OSCCTRL32_EN1K | BSCIF_OSCCTRL32_EN32K |
|
|
BSCIF_OSCCTRL32_OSC32EN;
|
|
|
|
putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET),
|
|
SAM_BSCIF_UNLOCK);
|
|
putreg32(regval, SAM_BSCIF_OSCCTRL32);
|
|
|
|
/* Wait for OSC32 to be ready */
|
|
|
|
while (getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enablerc80m
|
|
*
|
|
* Description:
|
|
* Initialiaze the 80 MHz RC oscillator per settings in the board.h header
|
|
* file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_RC80M
|
|
static inline void sam_enablerc80m(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Configure and enable RC80M */
|
|
|
|
regval = getreg32(SAM_SCIF_RC80MCR);
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RC80MCR_OFFSET),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(regval | SCIF_RC80MCR_EN, SAM_SCIF_RC80MCR);
|
|
|
|
/* Wait for OSC32 to be ready */
|
|
|
|
while (getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enablerc80m
|
|
*
|
|
* Description:
|
|
* Initialiaze the 12/8/4 RC fast oscillator per settings in the board.h
|
|
* header file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_RCFAST
|
|
static inline void sam_enablercfast(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Configure and enable RCFAST */
|
|
|
|
regval = getreg32(SAM_SCIF_RCFASTCFG);
|
|
regval &= ~SCIF_RCFASTCFG_FRANGE_MASK;
|
|
regval |= (SAM_RCFAST_RANGE | SCIF_RCFASTCFG_EN);
|
|
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(regval, SAM_SCIF_RCFASTCFG);
|
|
|
|
/* Wait for RCFAST to be ready */
|
|
|
|
while (getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enablerc1m
|
|
*
|
|
* Description:
|
|
* Initialiaze the 1M RC oscillator per settings in the board.h header
|
|
* file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_RC1M
|
|
static inline void sam_enablerc1m(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Configure and enable RC1M */
|
|
|
|
regval = getreg32(SAM_BSCIF_RC1MCR);
|
|
regval &= ~BSCIF_RCFASTCFG_FRANGE_MASK;
|
|
regval |= (SAM_RCFAST_RANGE | BSCIF_RCFASTCFG_EN);
|
|
|
|
putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET),
|
|
SAM_BSCIF_UNLOCK);
|
|
putreg32(regval | BSCIF_RC1MCR_CLKOEN, SAM_BSCIF_RC1MCR);
|
|
|
|
/* Wait for RCFAST to be ready */
|
|
|
|
while (getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enablerc32k
|
|
*
|
|
* Description:
|
|
* Initialiaze the 23KHz RC oscillator per settings in the board.h header
|
|
* file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_RC32K
|
|
static inline void sam_enablerc32k(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Configure and enable RC32K */
|
|
|
|
regval = getreg32(SAM_BSCIF_RC32KCR);
|
|
putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET),
|
|
SAM_BSCIF_UNLOCK);
|
|
putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, SAM_BSCIF_RC32KCR);
|
|
|
|
/* Wait for RCFAST to be ready */
|
|
|
|
while (getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enableglck9
|
|
*
|
|
* Description:
|
|
* Enable GLCK9.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef NEED_GLCK9
|
|
static inline void sam_enableglck9(void)
|
|
{
|
|
/* Enable the generic clock using the source specified in the board.h
|
|
* file. No division is used so that the GCLK9 frequency is the same
|
|
* as the source frequency.
|
|
*/
|
|
|
|
putreg32(SAM_GCLK9_SOURCE_VALUE | SCIF_GCCTRL_CEN, SAM_SCIF_GCCTRL9);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enablepll0 (and its helper sam_pll0putreg())
|
|
*
|
|
* Description:
|
|
* Initialiaze PLL0 settings per the definitions in the board.h file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef BOARD_SYSCLK_SOURCE_PLL0
|
|
static inline void sam_pll0putreg(uint32_t regval, uint32_t regaddr,
|
|
uint32_t regoffset)
|
|
{
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(regval, regaddr);
|
|
}
|
|
|
|
static inline void sam_enablepll0(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Clear the PLL0 control register */
|
|
|
|
sam_pll0putreg(0, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET);
|
|
|
|
/* Write the selected options */
|
|
|
|
regval = getreg32(SAM_SCIF_PLL0);
|
|
regval &= SCIF_PLL0_PLLOPT_MASK;
|
|
regval |= SAM_PLL0_OPTIONS;
|
|
sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET);
|
|
|
|
/* Set up the multiers and dividers */
|
|
|
|
regval = getreg32(SAM_SCIF_PLL0);
|
|
regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK);
|
|
regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) |
|
|
(BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) |
|
|
SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE;
|
|
sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET);
|
|
|
|
/* And, finally, enable PLL0 */
|
|
|
|
regval = getreg32(SAM_SCIF_PLL0);
|
|
regval |= SCIF_PLL_PLLEN;
|
|
sam_pll0putreg(regval, SAM_SCIF_PLL0, SAM_SCIF_PLL0_OFFSET);
|
|
|
|
/* Wait for PLL0 to become locked */
|
|
|
|
while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_PLL0LOCK) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_enabledfll0 (and its helper sam_dfll0_putreg32())
|
|
*
|
|
* Description:
|
|
* Initialiaze DFLL0 settings per the definitions in the board.h file.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef BOARD_SYSCLK_SOURCE_DFLL0
|
|
static inline void sam_dfll0_putreg32(uint32_t regval, uint32_t regaddr,
|
|
uint32_t regoffset)
|
|
{
|
|
/* Wait until DFLL0 is completes the last setting */
|
|
|
|
while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
|
|
|
|
/* Then unlock the register and write the next value */
|
|
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(regoffset),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(regval, regaddr);
|
|
}
|
|
|
|
static inline void sam_enabledfll0(void)
|
|
{
|
|
uint32_t regval;
|
|
uint32_t conf;
|
|
|
|
/* Set up generic clock source with specified reference clock
|
|
* and divider.
|
|
*/
|
|
|
|
putreg(0, SAM_SCIF_GCCTRL0);
|
|
|
|
/* Set the generic clock 0 source */
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL0);
|
|
regval &= ~SCIF_GCCTRL_OSCSEL_MASK;
|
|
regval |= SAM_DFLLO_REFCLK;
|
|
putreg32(regval, SAM_SCIF_GCCTRL0);
|
|
|
|
/* Get the generic clock 0 divider */
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL0);
|
|
regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK);
|
|
|
|
#if BOARD_DFLL0_DIV > 1
|
|
regval |= SCIF_GCCTRL_DIVEN;
|
|
regval |= SCIF_GCCTRL_DIV(((BOARD_DFLL0_DIV + 1) / 2) - 1);
|
|
#endif
|
|
|
|
putreg32(regval, SAM_SCIF_GCCTRL0);
|
|
|
|
/* Sync before reading a dfll conf register */
|
|
|
|
putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC);
|
|
while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
|
|
|
|
/* Select Closed Loop Mode */
|
|
|
|
conf = getreg(SAM_SCIF_DFLL0CONF);
|
|
conf &= ~SCIF_DFLL0CONF_RANGE_MASK;
|
|
conf |= SCIF_DFLL0CONF_MODE;
|
|
|
|
/* Select the DFLL0 Frequency Range */
|
|
|
|
#if BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE3
|
|
conf |= SCIF_DFLL0CONF_RANGE3;
|
|
#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE2
|
|
conf |= SCIF_DFLL0CONF_RANGE2;
|
|
#elif BOARD_DFLL0_FREQUENCY < SCIF_DFLL0CONF_MAX_RANGE1
|
|
conf |= SCIF_DFLL0CONF_RANGE1;
|
|
#else
|
|
conf |= SCIF_DFLL0CONF_RANGE0;
|
|
#ednif
|
|
|
|
/* Enable the reference generic clock 0 */
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL0);
|
|
regval |= SCIF_GCCTRL_CEN;
|
|
putreg32(regval, SAM_SCIF_GCCTRL0);
|
|
|
|
/* Enable DFLL0. Here we assume DFLL0RDY because the DFLL was disabled
|
|
* before this function was called.
|
|
*/
|
|
|
|
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET),
|
|
SAM_SCIF_UNLOCK);
|
|
putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF);
|
|
|
|
/* Configure DFLL0. Note that now we do have to wait for DFLL0RDY before
|
|
* every write.
|
|
*
|
|
* Set the initial coarse and fine step lengths to 4. If this is set
|
|
* too high, DFLL0 may fail to lock.
|
|
*/
|
|
|
|
sam_dfll0_putreg32((SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4),
|
|
SAM_SCIF_DFLL0STEP,
|
|
SAM_SCIF_DFLL0STEP_OFFSET);
|
|
|
|
/* Set the DFLL0 multipler register */
|
|
|
|
sam_dfll0_putreg32(BOARD_DFLL0_MUL, SAM_SCIF_DFLL0MUL,
|
|
SAM_SCIF_DFLL0MUL_OFFSET);
|
|
|
|
/* Set the multipler and spread spectrum generator control registers */
|
|
|
|
sam_dfll0_putreg32(0, SAM_SCIF_DFLL0SSG, SAM_SCIF_DFLL0SSG_OFFSET);
|
|
|
|
/* Finally, set the DFLL0 configuration */
|
|
|
|
sam_dfll0_putreg32(conf | SCIF_DFLL0CONF_EN,
|
|
SAM_SCIF_DFLL0CONF, SAM_SCIF_DFLL0CONF_OFFSET);
|
|
|
|
/* Wait until we are locked on the fine value */
|
|
|
|
while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0LOCKF) == 0);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: sam_setdividers
|
|
*
|
|
* Description:
|
|
* Configure derived clocks.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void sam_setdividers(void)
|
|
{
|
|
uint32_t cpusel;
|
|
uint32_t pbasel;
|
|
uint32_t pbbsel;
|
|
uint32_t pbcsel;
|
|
uint32_t pbdsel;
|
|
|
|
/* Get the register setting for each divider value */
|
|
|
|
#if BOARD_CPU_SHIFT > 0
|
|
cpusel = (PM_CPUSEL(BOARD_CPU_SHIFT - 1)) | PM_CPUSEL_DIV;
|
|
#else
|
|
cpusel = 0;
|
|
#endif
|
|
|
|
#if BOARD_PBA_SHIFT > 0
|
|
pbasel = (PM_PBSEL(BOARD_PBA_SHIFT - 1)) | PM_PBSEL_DIV;
|
|
#else
|
|
pbasel = 0;
|
|
#endif
|
|
|
|
#if BOARD_PBB_SHIFT >0
|
|
pbbsel = (PM_PBSEL(BOARD_PBB_SHIFT - 1)) | PM_PBSEL_DIV;
|
|
#else
|
|
pbbsel = 0;
|
|
#endif
|
|
|
|
#if BOARD_PBC_SHIFT > 0
|
|
pbcsel = (PM_PBSEL(BOARD_PBC_SHIFT - 1)) | PM_PBSEL_DIV;
|
|
#else
|
|
pbcsel = 0;
|
|
#endif
|
|
|
|
#if BOARD_PBD_SHIFT > 0
|
|
pbdsel = (PM_PBSEL(BOARD_PBD_SHIFT - 1)) | PM_PBSEL_DIV;
|
|
#else
|
|
pbdsel = 0;
|
|
#endif
|
|
|
|
/* Then set the divider values. */
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK);
|
|
putreg32(cpusel, SAM_PM_CPUSEL);
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), SAM_PM_UNLOCK);
|
|
putreg32(pbasel, SAM_PM_PBASEL);
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), SAM_PM_UNLOCK);
|
|
putreg32(pbbsel, SAM_PM_PBBSEL);
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), SAM_PM_UNLOCK);
|
|
putreg32(pbcsel, SAM_PM_PBCSEL);
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK);
|
|
putreg32(pbdsel, SAM_PM_PBDSEL);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sam_fws
|
|
*
|
|
* Description:
|
|
* Setup FLASH wait states.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void sam_fws(uint32_t cpuclock, uint32_t psm, bool fastwkup)
|
|
{
|
|
uint32_t regval;
|
|
|
|
regval = getreg32(SAM_FLASHCALW_FCR);
|
|
if (cpuclock > SAM_FLASHCALW_FWS0_MAXFREQ)
|
|
{
|
|
regval |= FLASHCALW_FCR_FWS;
|
|
}
|
|
else
|
|
{
|
|
regval &= ~FLASHCALW_FCR_FWS;
|
|
}
|
|
|
|
putreg32(regval, SAM_FLASHCALW_FCR);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sam_mainclk
|
|
*
|
|
* Description:
|
|
* Select the main clock.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void sam_mainclk(uint32_t mcsel)
|
|
{
|
|
uint32_t regval;
|
|
|
|
regval = getreg32(SAM_PM_MCCTRL);
|
|
regval &= ~PM_MCCTRL_MCSEL_MASK;
|
|
regval |= mcsel;
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_MCCTRL_OFFSET),
|
|
SAM_PM_UNLOCK);
|
|
putreg32(regval, SAM_PM_MCCTRL);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sam_setpsm (and its helper, sam_instantiatepsm())
|
|
*
|
|
* Description:
|
|
* Switch to the selected power scaling mode.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static __ramfunc__ void sam_instantiatepsm(Bpm *bpm, uint32_t regval)
|
|
{
|
|
/* Set the BMP PCOM register (containing the new power scaling mode) */
|
|
|
|
putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET),
|
|
SAM_BPM_UNLOCK);
|
|
putreg32(regval, SAM_BPM_PMCON);
|
|
|
|
/* Wait for new power scaling mode to become active. There should be
|
|
* timeout on this wait.
|
|
*/
|
|
|
|
while ((getreg32(SAM_BPM_SR) & BPM_INT_PSOK) == 0);
|
|
}
|
|
|
|
static inline void sam_setpsm(uint32_t psm)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Setup the PMCON register content fo the new power scaling mode */
|
|
|
|
regval = getreg32(SAM_BPM_PMCON);
|
|
regval &= ~BPM_PMCON_PS_MASK;
|
|
regval |= (psm | BPM_PMCON_PSCM | BPM_PMCON_PSCREQ);
|
|
|
|
/* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */
|
|
|
|
sam_instantiatepsm(bpm, regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sam_usbclock
|
|
*
|
|
* Description:
|
|
* Setup the USBB GCLK.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_USBDEV
|
|
static inline void sam_usbclock(void)
|
|
{
|
|
uint32_t regval = 0;
|
|
|
|
#if defined(SAM_CLOCK_USB_PLL0) || defined(SAM_CLOCK_USB_PLL1)
|
|
regval |= PM_GCCTRL_PLLSEL;
|
|
#endif
|
|
#if defined(SAM_CLOCK_USB_OSC1) || defined(SAM_CLOCK_USB_PLL1)
|
|
regval |= PM_GCCTRL_OSCSEL;
|
|
#endif
|
|
#if SAM_CLOCK_USB_DIV > 0
|
|
|
|
|
|
u_avr32_pm_gcctrl.GCCTRL.diven = diven;
|
|
u_avr32_pm_gcctrl.GCCTRL.div = div;
|
|
#endif
|
|
putreg32(regval, SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
|
|
|
|
/* Enable USB GCLK */
|
|
|
|
regval = getreg32(SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
|
|
regval |= PM_GCCTRL_CEN;
|
|
putreg32(regval, SAM_PM_GCCTRL(SAM_PM_GCLK_USBB))
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: sam_clockconfig
|
|
*
|
|
* Description:
|
|
* Called to initialize the SAM3/4. This does whatever setup is needed to
|
|
* put the SoC in a usable state. This includes the initialization of
|
|
* clocking using the settings in board.h.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void sam_clockconfig(void)
|
|
{
|
|
uint32_t regval;
|
|
uint32_t psm;
|
|
bool fastwkup;
|
|
|
|
/* Enable clocking to the PICOCACHE */
|
|
|
|
sam_picocache();
|
|
|
|
/* Configure dividers for derived clocks. These divider definitions must
|
|
* be provided in the board.h header file.
|
|
*/
|
|
|
|
sam_setdividers();
|
|
|
|
/* Select a power scaling mode and possible fast wakeup so that we get the
|
|
* best possible flash performance. The following table shows the maximum
|
|
* CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes
|
|
* (Table 42-30 in the big data sheet).
|
|
*
|
|
* ------- ------------------- ---------- ----------
|
|
* Power Flash Read Mode Flash Maximum
|
|
* Sclaing Wait Operating
|
|
* Mode HSEN HSDIS FASTWKUP States Frequency
|
|
* ------- ---- ----- -------- ---------- ----------
|
|
* PS0 X X 1 12MHz
|
|
* " " X 0 18MHz
|
|
* " " X 1 36MHz
|
|
* PS1 X X 1 12MHz
|
|
* " " X 0 8MHz
|
|
* " " X 1 12MHz
|
|
* PS2 X 0 24Mhz
|
|
* " " X 1 48MHz
|
|
* ------- ---- ----- -------- ---------- ----------
|
|
*/
|
|
|
|
#ifdef CONFIG_SAM34_FLASH_HSEN
|
|
/* The high speed FLASH mode has been enabled. Select power scaling
|
|
* mode 2, no fast wakeup.
|
|
*/
|
|
|
|
psm = BPM_PMCON_PS2;
|
|
fastwkup = false;
|
|
#else
|
|
/* Not high speed mode. Check if we can go to power scaling mode 1. */
|
|
|
|
if (BOARD_CPU_FREQUENCY <= FLASH_MAXFREQ_PS1_HSDIS_FWS1)
|
|
{
|
|
/* Yes.. Do we also need to enable fast wakeup? */
|
|
|
|
psm = BPM_PMCON_PS1;
|
|
if (BOARD_CPU_FREQUENCY > FLASH_MAXFREQ_PS1_HSDIS_FWS0)
|
|
{
|
|
/* Yes.. enable fast wakeup */
|
|
|
|
regval = getreg32(SAM_BPM_PMCON);
|
|
regval |= BPM_PMCON_FASTWKUP;
|
|
putreg32(BPM_UNLOCK_KEY(0xaa) | BPM_UNLOCK_ADDR(SAM_BPM_PMCON_OFFSET), SAM_BPM_UNLOCK);
|
|
putreg32(regval, SAM_BPM_PMCON);
|
|
|
|
/* We need to remember that we did this */
|
|
|
|
fastwkup = true;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
psm = BPM_PMCON_PS0;
|
|
}
|
|
#endif
|
|
|
|
/* Enable clock sources:
|
|
*
|
|
* OSC0: Might by the system clock or the source clock for PLL0 or DFLL0
|
|
* OSC32: Might be source clock for DFLL0
|
|
*/
|
|
|
|
#if NEED_OSC0
|
|
/* Enable OSC0 using the settings in board.h */
|
|
|
|
sam_enableosc0();
|
|
#endif
|
|
|
|
#ifdef NEED_OSC32K
|
|
/* Enable the 32KHz oscillator using the settings in board.h */
|
|
|
|
sam_enableosc32();
|
|
#endif
|
|
|
|
#ifdef NEED_OSC32K
|
|
/* Enable the 32KHz oscillator using the settings in board.h */
|
|
|
|
sam_enablerc80m();
|
|
#endif
|
|
|
|
#ifdef NEED_RCFAST
|
|
/* Enable the 12/8/4MHz RC fast oscillator using the settings in board.h */
|
|
|
|
sam_enablercrcfast();
|
|
#endif
|
|
|
|
#ifdef NEED_RC1M
|
|
/* Enable the 1MHz RC oscillator using the settings in board.h */
|
|
|
|
sam_enablerc1m();
|
|
#endif
|
|
|
|
#ifdef NEED_RC32K
|
|
/* Enable the 32KHz RC oscillator using the settings in board.h */
|
|
|
|
sam_enablerc32k();
|
|
#endif
|
|
|
|
#ifdef NEED_GLCK9
|
|
/* Enable the GLCK9 */
|
|
|
|
sam_enableglck9();
|
|
#endif
|
|
|
|
/* Switch to the system clock selected by the settings in the board.h
|
|
* header file.
|
|
*/
|
|
|
|
#if defined(BOARD_SYSCLK_SOURCE_RCSYS)
|
|
/* Since this function only executes at power up, we know that we are
|
|
* already running from RCSYS.
|
|
*/
|
|
|
|
// sam_mainclk(PM_MCCTRL_MCSEL_RCSYS);
|
|
#elif defined(BOARD_SYSCLK_SOURCE_OSC0)
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to OSC0 */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_OSC0);
|
|
|
|
#elif defined(BOARD_SYSCLK_SOURCE_PLL0)
|
|
|
|
/* Enable PLL0 using the settings in board.h */
|
|
|
|
sam_enablepll0();
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to PLL0 */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_PLL);
|
|
|
|
#elif defined(BOARD_SYSCLK_SOURCE_DFLL0)
|
|
|
|
/* Enable PLL0 using the settings in board.h */
|
|
|
|
sam_enabledfll0();
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to DFLL0 */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_DFLL);
|
|
|
|
#elif defined(BOARD_SYSCLK_SOURCE_RC80M)
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to RCM80 */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_RC80M);
|
|
|
|
#elif defined(BOARD_SYSCLK_SOURCE_FCFAST12M) || defined(BOARD_SYSCLK_SOURCE_FCFAST8M) || \
|
|
defined(BOARD_SYSCLK_SOURCE_FCFAST4M)
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to RCFAST */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_RCFAST);
|
|
|
|
#elif defined(BOARD_SYSCLK_SOURCE_RC1M)
|
|
|
|
/* Set up FLASH wait states */
|
|
|
|
sam_fws(BOARD_CPU_FREQUENCY, psm, fastwkup);
|
|
|
|
/* Then switch the main clock to RC1M */
|
|
|
|
sam_mainclk(PM_MCCTRL_MCSEL_RC1M);
|
|
|
|
#else
|
|
# error "No SYSCLK source provided"
|
|
#endif
|
|
|
|
/* Switch to the selected power scaling mode */
|
|
|
|
sam_setpsm(psm);
|
|
|
|
/* Enable all selected peripheral cloks */
|
|
|
|
sam_init_periphclks();
|
|
|
|
#ifdef CONFIG_USBDEV
|
|
void sam_usbclock();
|
|
#endif
|
|
}
|