402 lines
27 KiB
C
402 lines
27 KiB
C
/************************************************************************************************
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* arch/arm/src/lpc54xx/lpc54_sdmmc.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H
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#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/lpc54_memorymap.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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#define LPC54_TXFIFO_DEPTH 32
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#define LPC54_TXFIFO_WIDTH 4
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#define LPC54_RXFIFO_DEPTH 32
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#define LPC54_RXFIFO_WIDTH 4
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/* MCI register offsets (with respect to the MCI base) ******************************************/
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#define LPC54_SDMMC_CTRL_OFFSET 0x0000 /* Control register */
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#define LPC54_SDMMC_PWREN_OFFSET 0x0004 /* Power Enable Register */
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#define LPC54_SDMMC_CLKDIV_OFFSET 0x0008 /* Clock-divider register */
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#define LPC54_SDMMC_CLKENA_OFFSET 0x0010 /* Clock-enable register */
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#define LPC54_SDMMC_TMOUT_OFFSET 0x0014 /* Time-out register */
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#define LPC54_SDMMC_CTYPE_OFFSET 0x0018 /* Card-type register */
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#define LPC54_SDMMC_BLKSIZ_OFFSET 0x001c /* Block-size register */
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#define LPC54_SDMMC_BYTCNT_OFFSET 0x0020 /* Byte-count register */
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#define LPC54_SDMMC_INTMASK_OFFSET 0x0024 /* Interrupt-mask register */
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#define LPC54_SDMMC_CMDARG_OFFSET 0x0028 /* Command-argument register */
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#define LPC54_SDMMC_CMD_OFFSET 0x002c /* Command register */
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#define LPC54_SDMMC_RESP0_OFFSET 0x0030 /* Response-0 register */
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#define LPC54_SDMMC_RESP1_OFFSET 0x0034 /* Response-1 register */
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#define LPC54_SDMMC_RESP2_OFFSET 0x0038 /* Response-2 register */
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#define LPC54_SDMMC_RESP3_OFFSET 0x003c /* Response-3 register */
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#define LPC54_SDMMC_MINTSTS_OFFSET 0x0040 /* Masked interrupt-status register */
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#define LPC54_SDMMC_RINTSTS_OFFSET 0x0044 /* Raw interrupt-status register */
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#define LPC54_SDMMC_STATUS_OFFSET 0x0048 /* Status register */
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#define LPC54_SDMMC_FIFOTH_OFFSET 0x004c /* FIFO threshold register */
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#define LPC54_SDMMC_CDETECT_OFFSET 0x0050 /* Card-detect register value */
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#define LPC54_SDMMC_WRTPRT_OFFSET 0x0054 /* Write-protect register */
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#define LPC54_SDMMC_TCBCNT_OFFSET 0x005c /* Transferred CIU card byte count */
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#define LPC54_SDMMC_TBBCNT_OFFSET 0x0060 /* Transferred host to BIU-FIFO byte count */
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#define LPC54_SDMMC_DEBNCE_OFFSET 0x0064 /* Debounce count register */
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#define LPC54_SDMMC_RSTN_OFFSET 0x0078 /* Hardware Reset */
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#define LPC54_SDMMC_BMOD_OFFSET 0x0080 /* Bus Mode Register */
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#define LPC54_SDMMC_PLDMND_OFFSET 0x0084 /* Poll Demand Register */
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#define LPC54_SDMMC_DBADDR_OFFSET 0x0088 /* Descriptor List Base Address Register */
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#define LPC54_SDMMC_IDSTS_OFFSET 0x008c /* Internal DMAC Status Register */
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#define LPC54_SDMMC_IDINTEN_OFFSET 0x0090 /* Internal DMAC Interrupt Enable Register */
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#define LPC54_SDMMC_DSCADDR_OFFSET 0x0094 /* Current Host Descriptor Address Register */
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#define LPC54_SDMMC_BUFADDR_OFFSET 0x0098 /* Current Buffer Descriptor Address Register */
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#define LPC54_SDMMC_CARDTHRCTL_OFFSET 0x0100 /* Card threshold control */
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#define LPC54_SDMMC_BACKENDPWRL_OFFSET 0x0104 /* Power control */
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#define LPC54_SDMMC_DATA_OFFSET 0x0200 /* Data FIFO read/write (>=) */
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/* MCI register (virtual) addresses *************************************************************/
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#define LPC54_SDMMC_CTRL (LPC54_SDMMC_BASE + LPC54_SDMMC_CTRL_OFFSET)
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#define LPC54_SDMMC_PWREN (LPC54_SDMMC_BASE + LPC54_SDMMC_PWREN_OFFSET)
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#define LPC54_SDMMC_CLKDIV (LPC54_SDMMC_BASE + LPC54_SDMMC_CLKDIV_OFFSET)
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#define LPC54_SDMMC_CLKENA (LPC54_SDMMC_BASE + LPC54_SDMMC_CLKENA_OFFSET)
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#define LPC54_SDMMC_TMOUT (LPC54_SDMMC_BASE + LPC54_SDMMC_TMOUT_OFFSET)
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#define LPC54_SDMMC_CTYPE (LPC54_SDMMC_BASE + LPC54_SDMMC_CTYPE_OFFSET)
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#define LPC54_SDMMC_BLKSIZ (LPC54_SDMMC_BASE + LPC54_SDMMC_BLKSIZ_OFFSET)
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#define LPC54_SDMMC_BYTCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_BYTCNT_OFFSET)
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#define LPC54_SDMMC_INTMASK (LPC54_SDMMC_BASE + LPC54_SDMMC_INTMASK_OFFSET)
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#define LPC54_SDMMC_CMDARG (LPC54_SDMMC_BASE + LPC54_SDMMC_CMDARG_OFFSET)
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#define LPC54_SDMMC_CMD (LPC54_SDMMC_BASE + LPC54_SDMMC_CMD_OFFSET)
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#define LPC54_SDMMC_RESP0 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP0_OFFSET)
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#define LPC54_SDMMC_RESP1 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP1_OFFSET)
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#define LPC54_SDMMC_RESP2 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP2_OFFSET)
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#define LPC54_SDMMC_RESP3 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP3_OFFSET)
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#define LPC54_SDMMC_MINTSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_MINTSTS_OFFSET)
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#define LPC54_SDMMC_RINTSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_RINTSTS_OFFSET)
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#define LPC54_SDMMC_STATUS (LPC54_SDMMC_BASE + LPC54_SDMMC_STATUS_OFFSET)
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#define LPC54_SDMMC_FIFOTH (LPC54_SDMMC_BASE + LPC54_SDMMC_FIFOTH_OFFSET)
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#define LPC54_SDMMC_CDETECT (LPC54_SDMMC_BASE + LPC54_SDMMC_CDETECT_OFFSET)
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#define LPC54_SDMMC_WRTPRT (LPC54_SDMMC_BASE + LPC54_SDMMC_WRTPRT_OFFSET)
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#define LPC54_SDMMC_TCBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TCBCNT_OFFSET)
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#define LPC54_SDMMC_TBBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TBBCNT_OFFSET)
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#define LPC54_SDMMC_TBBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TBBCNT_OFFSET)
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#define LPC54_SDMMC_DEBNCE (LPC54_SDMMC_BASE + LPC54_SDMMC_DEBNCE_OFFSET)
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#define LPC54_SDMMC_RSTN (LPC54_SDMMC_BASE + LPC54_SDMMC_RSTN_OFFSET)
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#define LPC54_SDMMC_BMOD (LPC54_SDMMC_BASE + LPC54_SDMMC_BMOD_OFFSET)
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#define LPC54_SDMMC_PLDMND (LPC54_SDMMC_BASE + LPC54_SDMMC_PLDMND_OFFSET)
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#define LPC54_SDMMC_DBADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_DBADDR_OFFSET)
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#define LPC54_SDMMC_IDSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_IDSTS_OFFSET)
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#define LPC54_SDMMC_IDINTEN (LPC54_SDMMC_BASE + LPC54_SDMMC_IDINTEN_OFFSET)
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#define LPC54_SDMMC_DSCADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_DSCADDR_OFFSET)
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#define LPC54_SDMMC_BUFADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_BUFADDR_OFFSET)
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#define LPC54_SDMMC_CARDTHRCTL (LPC54_SDMMC_BASE + LPC54_SDMMC_CARDTHRCTL_OFFSET)
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#define LPC54_SDMMC_BACKENDPWRL (LPC54_SDMMC_BASE + LPC54_SDMMC_BACKENDPWRL_OFFSET)
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#define LPC54_SDMMC_DATA (LPC54_SDMMC_BASE + LPC54_SDMMC_DATA_OFFSET)
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/* MCI register bit definitions *****************************************************************/
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/* Control register CTRL */
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#define SDMMC_CTRL_CNTLRRESET (1 << 0) /* Bit 0: Reset Module controller */
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#define SDMMC_CTRL_FIFORESET (1 << 1) /* Bit 1: Reset to data FIFO to reset FIFO pointers */
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#define SDMMC_CTRL_DMARESET (1 << 2) /* Bit 2: Reset internal DMA interface control logic */
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/* Bit 3: Reserved */
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#define SDMMC_CTRL_INTENABLE (1 << 4) /* Bit 4: Enable interrupts */
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/* Bit 5: Reserved */
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#define SDMMC_CTRL_READWAIT (1 << 6) /* Bit 6: Assert read wait */
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#define SDMMC_CTRL_SENDIRQRESP (1 << 7) /* Bit 7: Send auto IRQ response */
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#define SDMMC_CTRL_ABORTREAD (1 << 8) /* Bit 8: Reset data state-machine (suspend sequence) */
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#define SDMMC_CTRL_SENDCCSD (1 << 9) /* Bit 9: Send CCSD to CE-ATA device */
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#define SDMMC_CTRL_AUTOSTOP (1 << 10) /* Bit 10: Send STOP after CCSD to CE-ATA device */
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#define SDMMC_CTRL_CEATAINT (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */
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/* Bits 12-15: Reserved */
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#define SDMMC_CTRL_CDVA0 (1 << 16) /* Bit 16: Controls SD_VOLT0 pin */
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#define SDMMC_CTRL_CDVA1 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */
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#define SDMMC_CTRL_CDVA2 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */
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/* Bits 19-23: Reserved */
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/* Bit 24: Reserved - always write it as 0 */
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#define SDMMC_CTRL_INTDMA (1 << 25) /* Bit 25: SD/MMC DMA use */
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/* Bits 26-31: Reserved */
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/* Power Enable Register (PWREN) */
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#define SDMMC_PWREN (1 << 0) /* Bit 0: Power on/off switch */
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/* Bits 1-31: Reserved */
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/* Clock divider register CLKDIV
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*
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* Clock division is 2*n. For example, value of 0 means divide by 2 * 0 = 0 (no division,
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* bypass), value of 1 means divide by 2 * 1 = 2, value of 255 means divide by 2 * 255 = 510,
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* and so on.
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*/
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#define SDMMC_CLKDIV0_SHIFT (0) /* Bits 0-7: Clock divider 0 value */
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#define SDMMC_CLKDIV0_MASK (255 << SDMMC_CLKDIV0_SHIFT)
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# define SDMMC_CLKDIV0(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV0_SHIFT)
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/* Bits 8-31: Reserved */
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/* Clock enable register CLKENA */
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#define SDMMC_CLKENA_ENABLE (1 << 0) /* Bit 0: Clock enable */
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/* Bits 1-15: Reserved */
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#define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */
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/* Bits 17-31: Reserved */
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/* Timeout register TMOUT */
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#define SDMMC_TMOUT_RESPONSE_SHIFT (0) /* Bits 0-7: Response timeout value */
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#define SDMMC_TMOUT_RESPONSE_MASK (255 << SDMMC_TMOUT_RESPONSE_SHIFT)
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#define SDMMC_TMOUT_DATA_SHIFT (8) /* Bits 8-31: Data Read Timeout value */
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#define SDMMC_TMOUT_DATA_MASK (0x00ffffff << SDMMC_TMOUT_DATA_SHIFT)
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/* Card type register CTYPE */
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#define SDMMC_CTYPE_WIDTH1 (0) /* 1-bit mode */
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#define SDMMC_CTYPE_WIDTH4 (1 << 0) /* Bit 0: 4-bit mode */
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/* Bits 1-15: Reserved */
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#define SDMMC_CTYPE_WIDTH8 (1 << 16) /* Bit 16: 8-bit mode */
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/* Bits 17-31: Reserved */
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/* Blocksize register BLKSIZ */
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#define SDMMC_BLKSIZ_SHIFT (0) /* Bits 0-15: Block size */
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#define SDMMC_BLKSIZ_MASK (0xffff << SDMMC_BLKSIZ_SHIFT)
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/* Bits 16-31: Reserved */
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/* Interrupt mask register INTMASK
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* Masked interrupt status register MINTSTS
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* Raw interrupt status register RINTSTS
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*/
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#define SDMMC_INT_CDET (1 << 0) /* Bit 0: Card detect */
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#define SDMMC_INT_RE (1 << 1) /* Bit 1: Response error */
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#define SDMMC_INT_CDONE (1 << 2) /* Bit 2: Command done */
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#define SDMMC_INT_DTO (1 << 3) /* Bit 3: Data transfer over */
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#define SDMMC_INT_TXDR (1 << 4) /* Bit 4: Transmit FIFO data request */
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#define SDMMC_INT_RXDR (1 << 5) /* Bit 5: Receive FIFO data request */
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#define SDMMC_INT_RCRC (1 << 6) /* Bit 6: Response CRC error */
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#define SDMMC_INT_DCRC (1 << 7) /* Bit 7: Data CRC error */
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#define SDMMC_INT_RTO (1 << 8) /* Bit 8: Response timeout */
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#define SDMMC_INT_DRTO (1 << 9) /* Bit 9: Data read timeout */
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#define SDMMC_INT_HTO (1 << 10) /* Bit 10: Data starvation-by-cpu timeout */
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#define SDMMC_INT_FRUN (1 << 11) /* Bit 11: FIFO underrun/overrun error */
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#define SDMMC_INT_HLE (1 << 12) /* Bit 12: Hardware locked write error */
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#define SDMMC_INT_SBE (1 << 13) /* Bit 13: Start-bit error */
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#define SDMMC_INT_ACD (1 << 14) /* Bit 14: Auto command done */
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#define SDMMC_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */
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#define SDMMC_INT_SDMMC (1 << 16) /* Bit 16: SD/MMC interrupt */
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/* Bits 17-31: Reserved */
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#define SDMMC_INT_ALL (0x1ffff)
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/* Command register CMD */
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#define SDMMC_CMD_CMDINDEX_SHIFT (0) /* Bits 0-5: 5:0 Command index */
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#define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT)
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#define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */
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#define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */
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#define SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 6-7: Response expected */
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#define SDMMC_CMD_WAITRESP_MASK (3 << SDMMC_CMD_WAITRESP_SHIFT)
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# define SDMMC_CMD_NORESPONSE (0 << SDMMC_CMD_WAITRESP_SHIFT) /* x0: No response */
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# define SDMMC_CMD_SHORTRESPONSE (1 << SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
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# define SDMMC_CMD_LONGRESPONSE (3 << SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
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#define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */
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#define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */
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#define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */
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#define SDMMC_CMD_XFRMODE (1 << 11) /* Bit 11: Stream data transfer command */
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#define SDMMC_CMD_AUTOSTOP (1 << 12) /* Bit 12: Send stop command at end of data transfer */
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#define SDMMC_CMD_WAITPREV (1 << 13) /* Bit 13: Wait previous transfer complete before sending */
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#define SDMMC_CMD_STOPABORT (1 << 14) /* Bit 14: Stop current data transfer */
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#define SDMMC_CMD_SENDINIT (1 << 15) /* Bit 15: Send initialization sequence before command */
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/* Bits 16-20: Reserved */
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#define SDMMC_CMD_UPDCLOCK (1 << 21) /* Bit 21: Update clock register value (no command) */
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#define SDMMC_CMD_READCEATA (1 << 22) /* Bit 22: Performing read access on CE-ATA device */
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#define SDMMC_CMD_CCSEXPTD (1 << 23) /* Bit 23: Expect command completion from CE-ATA device */
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#define SDMMC_CMD_ENABOOT (1 << 24) /* Bit 24: Enable Boot */
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#define SDMMC_CMD_BACKEXPTED (1 << 25) /* Bit 25: Expect Boot Acknowledge */
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#define SDMMC_CMD_DISBOOT (1 << 26) /* Bit 26: Disable Boot */
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#define SDMMC_CMD_BOOTMODE (1 << 27) /* Bit 27: Boot Mode */
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#define SDMMC_CMD_VSWITCH (1 << 28) /* Bit 28: Voltage switch bit */
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#define SDMMC_CMD_USEHOLD (1 << 29) /* Bit 29: Use Hold Registert */
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/* Bit 30: Reserved */
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#define SDMMC_CMD_STARTCMD (1 << 31) /* Bit 31: Start command */
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/* Status register STATUS */
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#define SDMMC_STATUS_RXWMARK (1 << 0) /* Bit 0: FIFO reached Receive watermark level */
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#define SDMMC_STATUS_TXWMARK (1 << 1) /* Bit 1: FIFO reached Transmit watermark level */
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#define SDMMC_STATUS_FIFOEMPTY (1 << 2) /* Bit 2: FIFO is empty */
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#define SDMMC_STATUS_FIFOFULL (1 << 3) /* Bit 3: FIFO is full */
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#define SDMMC_STATUS_FSMSTATE_SHIFT (4) /* Bits 4-7: 7:4 Command FSM states */
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#define SDMMC_STATUS_FSMSTATE_MASK (15 << SDMMC_STATUS_FSMSTATE_SHIFT)
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# define SDMMC_STATUS_FSMSTATE_IDLE (0 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Idle */
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# define SDMMC_STATUS_FSMSTATE_INIT (1 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Send init sequence */
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# define SDMMC_STATUS_FSMSTATE_TXSTART (2 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd start bit */
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# define SDMMC_STATUS_FSMSTATE_TXTXBIT (3 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd tx bit */
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# define SDMMC_STATUS_FSMSTATE_TXCMDARG (4 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd index + arg */
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# define SDMMC_STATUS_FSMSTATE_TXCMDCRC (5 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd crc7 */
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# define SDMMC_STATUS_FSMSTATE_TXEND (6 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd end bit */
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# define SDMMC_STATUS_FSMSTATE_RXSTART (7 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp start bit */
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# define SDMMC_STATUS_FSMSTATE_RXIRQ (8 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp IRQ response */
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# define SDMMC_STATUS_FSMSTATE_RXTXBIT (9 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp tx bit */
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# define SDMMC_STATUS_FSMSTATE_RXCMD (10 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp cmd idx */
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# define SDMMC_STATUS_FSMSTATE_RXRESP (11 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp data */
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# define SDMMC_STATUS_FSMSTATE_RXRESPCRC (12 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp crc7 */
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# define SDMMC_STATUS_FSMSTATE_RXEND (13 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp end bit */
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# define SDMMC_STATUS_FSMSTATE_WAITNCC (14 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Cmd path wait NCC */
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# define SDMMC_STATUS_FSMSTATE_WAITTURN (15 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Wait; CMD-to-resp turnaround */
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#define SDMMC_STATUS_DAT3 (1 << 8) /* Bit 8: DAT3=1: Card present */
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#define SDMMC_STATUS_DATABUSY (1 << 9) /* Bit 9: Card data busy */
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#define SDMMC_STATUS_MCBUSY (1 << 10) /* Bit 10: Data transmit/receive state machine busy */
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#define SDMMC_STATUS_RESPINDEX_SHIFT (11) /* Bits 11-16: Index of previous response */
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#define SDMMC_STATUS_RESPINDEX_MASK (63 << SDMMC_STATUS_RESPINDEX_SHIFT)
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#define SDMMC_STATUS_FIFOCOUNT_SHIFT (17) /* Bits 17-29: FIFO count */
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#define SDMMC_STATUS_FIFOCOUNT_MASK (0x1fff << SDMMC_STATUS_FIFOCOUNT_SHIFT)
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#define SDMMC_STATUS_DMAACK (1 << 30) /* Bit 30: DMA acknowledge signal state */
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#define SDMMC_STATUS_DMAREQ (1 << 31) /* Bit 31: DMA request signal state */
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/* FIFO threshold register FIFOTH */
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#define SDMMC_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */
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#define SDMMC_FIFOTH_TXWMARK_MASK (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT)
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# define SDMMC_FIFOTH_TXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_TXWMARK_SHIFT)
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/* Bits 12-15: Reserved */
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#define SDMMC_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */
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#define SDMMC_FIFOTH_RXWMARK_MASK (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT)
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# define SDMMC_FIFOTH_RXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_RXWMARK_SHIFT)
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#define SDMMC_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */
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#define SDMMC_FIFOTH_DMABURST_MASK (7 << SDMMC_FIFOTH_DMABURST_SHIFT)
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# define SDMMC_FIFOTH_DMABURST_1XFR (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */
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# define SDMMC_FIFOTH_DMABURST_4XFRS (1 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 4 transfers */
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# define SDMMC_FIFOTH_DMABURST_8XFRS (2 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 8 transfers */
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# define SDMMC_FIFOTH_DMABURST_16XFRS (3 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 16 transfers */
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# define SDMMC_FIFOTH_DMABURST_32XFRS (4 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 32 transfers */
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# define SDMMC_FIFOTH_DMABURST_64XFRS (5 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 64 transfers */
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# define SDMMC_FIFOTH_DMABURST_128XFRS (6 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 128 transfers */
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# define SDMMC_FIFOTH_DMABURST_256XFRS (7 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 256 transfers */
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/* Bit 31: Reserved */
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/* Card detect register CDETECT */
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#define SDMMC_CDETECT_NOTPRESENT (1 << 0) /* Bit 0: Card detect */
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/* Bit 1-31: Reserved */
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/* Write protect register WRTPRT */
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#define SDMMC_WRTPRT_PROTECTED (1 << 0) /* Bit 0: Write protect */
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/* Bit 1-31: Reserved */
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/* Debounce count register */
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#define SDMMC_DEBNCE_MASK 0x00ffffff /* Bits 0-23: Debounce count */
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/* Bit 24-31: Reserved */
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/* Hardware Reset */
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#define SDMMC_RSTN (1 << 0) /* Bit 0: Hardware reset */
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/* Bit 1-31: Reserved */
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/* Bus Mode Register */
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#define SDMMC_BMOD_SWR (1 << 0) /* Bit 0: Software Reset */
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#define SDMMC_BMOD_FB (1 << 1) /* Bit 1: Fixed Burst */
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#define SDMMC_BMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */
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#define SDMMC_BMOD_DSL_MASK (31 << SDMMC_BMOD_DSL_SHIFT)
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# define SDMMC_BMOD_DSL(n) ((uint32_t)(n) << SDMMC_BMOD_DSL_SHIFT)
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#define SDMMC_BMOD_DE (1 << 7) /* Bit 7: SD/MMC DMA Enable */
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#define SDMMC_BMOD_PBL_SHIFT (8) /* Bits 8-10: Programmable Burst Length */
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#define SDMMC_BMOD_PBL_MASK (7 << SDMMC_BMOD_PBL_SHIFT)
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# define SDMMC_BMOD_PBL_1XFRS (0 << SDMMC_BMOD_PBL_SHIFT) /* 1 transfer */
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# define SDMMC_BMOD_PBL_4XFRS (1 << SDMMC_BMOD_PBL_SHIFT) /* 4 transfers */
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# define SDMMC_BMOD_PBL_8XFRS (2 << SDMMC_BMOD_PBL_SHIFT) /* 8 transfers */
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# define SDMMC_BMOD_PBL_16XFRS (3 << SDMMC_BMOD_PBL_SHIFT) /* 16 transfers */
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# define SDMMC_BMOD_PBL_32XFRS (4 << SDMMC_BMOD_PBL_SHIFT) /* 32 transfers */
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# define SDMMC_BMOD_PBL_64XFRS (5 << SDMMC_BMOD_PBL_SHIFT) /* 64 transfers */
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# define SDMMC_BMOD_PBL_128XFRS (6 << SDMMC_BMOD_PBL_SHIFT) /* 128 transfers */
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# define SDMMC_BMOD_PBL_256XFRS (7 << SDMMC_BMOD_PBL_SHIFT) /* 256 transfers */
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/* Bits 11-31: Reserved */
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/* Internal DMAC Status Register */
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#define SDMMC_IDSTS_TI (1 << 0) /* Bit 0: Transmit Interrupt */
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#define SDMMC_IDSTS_RI (1 << 1) /* Bit 1: Receive Interrupt */
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#define SDMMC_IDSTS_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */
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/* Bit 3: Reserved */
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#define SDMMC_IDSTS_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */
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#define SDMMC_IDSTS_CES (1 << 5) /* Bit 5: Card Error Summary */
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/* Bits 6-7: Reserved */
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#define SDMMC_IDSTS_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */
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#define SDMMC_IDSTS_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */
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#define SDMMC_IDSTS_EB_SHIFT (10) /* Bits 10-12: Error Bits */
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#define SDMMC_IDSTS_EB_MASK (7 << SDMMC_IDSTS_EB_SHIFT)
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# define SDMMC_IDSTS_EB_TXHABORT (1 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during transmission */
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# define SDMMC_IDSTS_EB_RXHABORT (2 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during reception */
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#define SDMMC_IDSTS_FSM_SHIFT (13) /* Bits 13-16: DMAC state machine present state */
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#define SDMMC_IDSTS_FSM_MASK (15 << SDMMC_IDSTS_FSM_SHIFT)
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# define SDMMC_IDSTS_FSM_DMAIDLE (0 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_IDLE*/
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# define SDMMC_IDSTS_FSM_DMASUSP (1 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_SUSPEND */
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# define SDMMC_IDSTS_FSM_DESCRD (2 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_RD */
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# define SDMMC_IDSTS_FSM_DESCCHK (3 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CHK */
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# define SDMMC_IDSTS_FSM_DMARDREQW (4 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD_REQ_WAIT */
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# define SDMMC_IDSTS_FSM_DMAWRREQW (5 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR_REQ_WAIT */
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# define SDMMC_IDSTS_FSM_DMARD (6 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD */
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# define SDMMC_IDSTS_FSM_DMAWR (7 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR */
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# define SDMMC_IDSTS_FSM_DMACLOSE (8 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CLOSE */
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/* Bits 17-31: Reserved */
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/* Internal DMAC Interrupt Enable Register */
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#define SDMMC_IDINTEN_TI (1 << 0) /* Bit 0: Transmit Interrupt */
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#define SDMMC_IDINTEN_RI (1 << 1) /* Bit 1: Receive Interrupt */
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#define SDMMC_IDINTEN_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */
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/* Bit 3: Reserved */
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#define SDMMC_IDINTEN_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */
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#define SDMMC_IDINTEN_CES (1 << 5) /* Bit 5: Card Error Summary */
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/* Bits 6-7: Reserved */
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#define SDMMC_IDINTEN_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */
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#define SDMMC_IDINTEN_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */
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/* Bits 10-31: Reserved */
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#define SDMMC_IDINTEN_ALL 0x00000333
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/* Card threshold control */
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#define SDMMC_CARDTHRCTL_CARDRDTHREN (1 << 0) /* Bit 0: Card read threshold enable */
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#define SDMMC_CARDTHRCTL_BSYCLRINTEN (1 << 1) /* Bit 1: Busy clear interrupt enable */
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/* Bits 1-15: Reserved */
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#define SDMMC_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16) /* Bits 16-23: Card threshold size */
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#define SDMMC_CARDTHRCTL_CARDTHRESHOLD_MASK (0xff << SDMMC_CARDTHRCTL_CARDTHRESHOLD_SHIFT)
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/* Power control */
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#define SDMMC_BACKENDPWRL (1 << 0) /* Bit 0: Back-end Power control for card application. */
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H */
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