3a262416d6
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
271 lines
17 KiB
C
271 lines
17 KiB
C
/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_mci.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H
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#define __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "lpc31_memorymap.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* MCI register base address offset into the MCI domain *****************************************/
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#define LPC31_MCI_VBASE (LPC31_MCI_VSECTION)
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#define LPC31_MCI_PBASE (LPC31_MCI_PSECTION)
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/* MCI register offsets (with respect to the MCI base) ******************************************/
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#define LPC31_MCI_CTRL_OFFSET 0x000 /* Control register */
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#define LPC31_MCI_PWREN_OFFSET 0x004 /* Reserved */
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#define LPC31_MCI_CLKDIV_OFFSET 0x008 /* Clock-divider register */
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#define LPC31_MCI_CLKSRC_OFFSET 0x00c /* Clock-source register */
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#define LPC31_MCI_CLKENA_OFFSET 0x010 /* Clock-enable register */
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#define LPC31_MCI_TMOUT_OFFSET 0x014 /* Time-out register */
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#define LPC31_MCI_CTYPE_OFFSET 0x018 /* Card-type register */
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#define LPC31_MCI_BLKSIZ_OFFSET 0x01c /* Block-size register */
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#define LPC31_MCI_BYTCNT_OFFSET 0x020 /* Byte-count register */
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#define LPC31_MCI_INTMASK_OFFSET 0x024 /* Interrupt-mask register */
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#define LPC31_MCI_CMDARG_OFFSET 0x028 /* Command-argument register */
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#define LPC31_MCI_CMD_OFFSET 0x02c /* Command register */
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#define LPC31_MCI_RESP0_OFFSET 0x030 /* Response-0 register */
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#define LPC31_MCI_RESP1_OFFSET 0x034 /* Response-1register */
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#define LPC31_MCI_RESP2_OFFSET 0x038 /* Response-2 register */
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#define LPC31_MCI_RESP3_OFFSET 0x03c /* Response-3 register */
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#define LPC31_MCI_MINTSTS_OFFSET 0x040 /* Masked interrupt-status register */
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#define LPC31_MCI_RINTSTS_OFFSET 0x044 /* Raw interrupt-status register */
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#define LPC31_MCI_STATUS_OFFSET 0x048 /* Status register */
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#define LPC31_MCI_FIFOTH_OFFSET 0x04c /* FIFO threshold register */
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#define LPC31_MCI_CDETECT_OFFSET 0x050 /* Card-detect register value */
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#define LPC31_MCI_WRTPRT_OFFSET 0x054 /* Write-protect register */
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/* 0x58: Reserved */
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#define LPC31_MCI_TCBCNT_OFFSET 0x05c /* Transferred CIU card byte count */
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#define LPC31_MCI_TBBCNT_OFFSET 0x060 /* Transferred cpu/DMA to/from BIU-FIFO byte count */
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/* 0x064-0x0ff: Reserved */
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#define LPC31_MCI_DATA_OFFSET 0x100 /* Data FIFO read/write (>=) */
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/* MCI register (virtual) addresses *************************************************************/
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#define LPC31_MCI_CTRL (LPC31_MCI_VBASE+LPC31_MCI_CTRL_OFFSET)
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#define LPC31_MCI_PWREN (LPC31_MCI_VBASE+LPC31_MCI_PWREN_OFFSET)
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#define LPC31_MCI_CLKDIV (LPC31_MCI_VBASE+LPC31_MCI_CLKDIV_OFFSET)
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#define LPC31_MCI_CLKSRC (LPC31_MCI_VBASE+LPC31_MCI_CLKSRC_OFFSET)
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#define LPC31_MCI_CLKENA (LPC31_MCI_VBASE+LPC31_MCI_CLKENA_OFFSET)
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#define LPC31_MCI_TMOUT (LPC31_MCI_VBASE+LPC31_MCI_TMOUT_OFFSET)
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#define LPC31_MCI_CTYPE (LPC31_MCI_VBASE+LPC31_MCI_CTYPE_OFFSET)
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#define LPC31_MCI_BLKSIZ (LPC31_MCI_VBASE+LPC31_MCI_BLKSIZ_OFFSET)
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#define LPC31_MCI_BYTCNT (LPC31_MCI_VBASE+LPC31_MCI_BYTCNT_OFFSET)
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#define LPC31_MCI_INTMASK (LPC31_MCI_VBASE+LPC31_MCI_INTMASK_OFFSET)
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#define LPC31_MCI_CMDARG (LPC31_MCI_VBASE+LPC31_MCI_CMDARG_OFFSET)
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#define LPC31_MCI_CMD (LPC31_MCI_VBASE+LPC31_MCI_CMD_OFFSET)
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#define LPC31_MCI_RESP0 (LPC31_MCI_VBASE+LPC31_MCI_RESP0_OFFSET)
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#define LPC31_MCI_RESP1 (LPC31_MCI_VBASE+LPC31_MCI_RESP1_OFFSET)
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#define LPC31_MCI_RESP2 (LPC31_MCI_VBASE+LPC31_MCI_RESP2_OFFSET)
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#define LPC31_MCI_RESP3 (LPC31_MCI_VBASE+LPC31_MCI_RESP3_OFFSET)
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#define LPC31_MCI_MINTSTS (LPC31_MCI_VBASE+LPC31_MCI_MINTSTS_OFFSET)
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#define LPC31_MCI_RINTSTS (LPC31_MCI_VBASE+LPC31_MCI_RINTSTS_OFFSET)
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#define LPC31_MCI_STATUS (LPC31_MCI_VBASE+LPC31_MCI_STATUS_OFFSET)
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#define LPC31_MCI_FIFOTH (LPC31_MCI_VBASE+LPC31_MCI_FIFOTH_OFFSET)
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#define LPC31_MCI_CDETECT (LPC31_MCI_VBASE+LPC31_MCI_CDETECT_OFFSET)
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#define LPC31_MCI_WRTPRT (LPC31_MCI_VBASE+LPC31_MCI_WRTPRT_OFFSET)
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#define LPC31_MCI_TCBCNT (LPC31_MCI_VBASE+LPC31_MCI_TCBCNT_OFFSET)
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#define LPC31_MCI_TBBCNT (LPC31_MCI_VBASE+LPC31_MCI_TBBCNT_OFFSET)
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#define LPC31_MCI_DATA (LPC31_MCI_VBASE+LPC31_MCI_DATA_OFFSET)
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/* MCI register bit definitions *****************************************************************/
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/* Control register CTRL, address 0x18000000 */
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#define MCI_CTRL_CEATAINT (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */
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#define MCI_CTRL_AUTOSTOP (1 << 10) /* Bit 10: Send STOP after CCSD to CE-ATA device */
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#define MCI_CTRL_SENDCCSD (1 << 9) /* Bit 9: Send CCSD to CE-ATA device */
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#define MCI_CTRL_ABORTREAD (1 << 8) /* Bit 8: Reset data state-machine (suspend sequence) */
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#define MCI_CTRL_SENDIRQRESP (1 << 7) /* Bit 7: Send auto IRQ response */
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#define MCI_CTRL_READWAIT (1 << 6) /* Bit 6: Assert read wait */
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#define MCI_CTRL_DMAENABLE (1 << 5) /* Bit 5: Enable DMA transfer mode */
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#define MCI_CTRL_INTENABLE (1 << 4) /* Bit 4: Enable interrupts */
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#define MCI_CTRL_DMARESET (1 << 2) /* Bit 2: Reset internal DMA interface control logic */
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#define MCI_CTRL_FIFORESET (1 << 1) /* Bit 1: Reset to data FIFO To reset FIFO pointers */
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#define MCI_CTRL_CNTLRRESET (1 << 0) /* Bit 0: Reset Module controller */
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/* Clock divider register CLKDIV, address 0x18000008 */
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#define MCI_CLKDIV_SHIFT (0) /* Bits 0-7: Clock divider */
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#define MCI_CLKDIV_MASK (255 << MCI_CLKDIV_SHIFT)
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/* Clock source register CLKSRC, address 0x1800000c */
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#define MCI_CLKSRC_SHIFT (0) /* Bits 0-1: Must be zero */
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#define MCI_CLKSRC_MASK (3 << MCI_CLKSRC_SHIFT)
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/* Clock enable register CLKENA, address 0x18000010 */
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#define MCI_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */
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#define MCI_CLKENA_EMABLE (1 << 0) /* Bit 0: Clock enable */
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/*Timeout register TMOUT, address 0x18000014 */
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#define MCI_TMOUT_DATA_SHIFT (8) /* Bits 8-31: Data Read Timeout value */
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#define MCI_TMOUT_DATA_MASK (0x00ffffff << MCI_TMOUT_DATA_SHIFT)
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#define MCI_TMOUT_RESPONSE_SHIFT (0) /* Bits 0-7: Response timeout value */
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#define MCI_TMOUT_RESPONSE_MASK (255 << MCI_TMOUT_RESPONSE_SHIFT)
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/* Card type register CTYPE, address 0x18000018 */
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#define MCI_CTYPE_WIDTH8 (1 << 16) /* Bit 16: 8-bit mode */
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#define MCI_CTYPE_WIDTH4 (1 << 0) /* Bit 0: 4-bit mode */
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/* Blocksize register BLKSIZ, address 0x1800001c */
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#define MCI_BLKSIZ_SHIFT (0) /* Bits 0-15: Block size */
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#define MCI_BLKSIZ_MASK (0xffff << MCI_BLKSIZ_SHIFT)
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/* Interrupt mask register INTMASK, address 0x18000024
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* Masked interrupt status register MINTSTS, address 0x18000040
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* Raw interrupt status register RINTSTS, address 0x18000044
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*/
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#define MCI_INT_SDIO (1 << 16) /* Bit 16: Mask SDIO interrupt */
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#define MCI_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */
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#define MCI_INT_ACD (1 << 14) /* Bit 14: Auto command done */
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#define MCI_INT_SBE (1 << 13) /* Bit 13: Start-bit error */
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#define MCI_INT_HLE (1 << 12) /* Bit 12: Hardware locked write error */
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#define MCI_INT_FRUN (1 << 11) /* Bit 11: FIFO underrun/overrun error */
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#define MCI_INT_HTO (1 << 10) /* Bit 10: Data starvation-by-cpu timeout */
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#define MCI_INT_DRTO (1 << 9) /* Bit 9: Data read timeout */
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#define MCI_INT_RTO (1 << 8) /* Bit 8: Response timeout */
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#define MCI_INT_DCRC (1 << 7) /* Bit 7: Data CRC error */
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#define MCI_INT_RCRC (1 << 6) /* Bit 6: Response CRC error */
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#define MCI_INT_RXDR (1 << 5) /* Bit 5: Receive FIFO data request */
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#define MCI_INT_TXDR (1 << 4) /* Bit 4: Transmit FIFO data request */
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#define MCI_INT_DTO (1 << 3) /* Bit 3: Data transfer over */
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#define MCI_INT_CD (1 << 2) /* Bit 2: Command done */
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#define MCI_INT_RE (1 << 1) /* Bit 1: Response error */
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#define MCI_INT_CD (1 << 0) /* Bit 0: Card detect */
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#define MCI_INT_ALL (0x1ffff)
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/* Command register CMD, address 0x1800002c */
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#define MCI_CMD_STARTCMD (1 << 31) /* Bit 31: Start command */
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#define MCI_CMD_CCSEXPTD (1 << 23) /* Bit 23: Expect command completion from CE-ATA device */
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#define MCI_CMD_READCEATA (1 << 22) /* Bit 22: Performing read access on CE-ATA device */
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#define MCI_CMD_UPDCLOCK (1 << 21) /* Bit 21: Update clock register value (no command) */
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#define MCI_CMD_SENDINIT (1 << 15) /* Bit 15: Send initialization sequence before command */
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#define MCI_CMD_STOPABORT (1 << 14) /* Bit 14: Stop current data transfer */
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#define MCI_CMD_WAITPREV (1 << 13) /* Bit 13: Wait previous transfer complete before sending */
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#define MCI_CMD_AUTOSTOP (1 << 12) /* Bit 12: Send stop command at end of data transfer */
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#define MCI_CMD_XFRMODE (1 << 11) /* Bit 11: Stream data transfer command */
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#define MCI_CMD_WRITE (1 << 10) /* Bit 10: Write to card */
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#define MCI_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */
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#define MCI_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */
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#define MCI_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */
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#define MCI_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */
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#define MCI_CMD_CMDINDEX_SHIFT (0) /* Bits 0-5: 5:0 Command index */
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#define MCI_CMD_CMDINDEX_MASK (63 << MCI_CMD_CMDINDEX_SHIFT)
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/* Status register STATUS, address 0x18000048 */
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#define MCI_STATUS_DMAREQ (1 << 31) /* Bit 31: DMA request signal state */
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#define MCI_STATUS_DMAACK (1 << 30) /* Bit 30: DMA acknowledge signal state */
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#define MCI_STATUS_FIFOCOUNT_SHIFT (17) /* Bits 17-29: FIFO count */
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#define MCI_STATUS_FIFOCOUNT_MASK (0x1fff << MCI_STATUS_FIFOCOUNT_SHIFT)
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#define MCI_STATUS_RESPINDEX_SHIFT (11) /* Bits 11-16: Index of previous response */
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#define MCI_STATUS_RESPINDEX_MASK (63 << MCI_STATUS_RESPINDEX_SHIFT)
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#define MCI_STATUS_MCBUSY (1 << 10) /* Bit 10: Data transmit/receive state machine busy */
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#define MCI_STATUS_DATABUSY (1 << 9) /* Bit 9: Card data busy */
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#define MCI_STATUS_DAT3 (1 << 8) /* Bit 8: DAT3=1: Card present */
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#define MCI_STATUS_FSMSTATE_SHIFT (4) /* Bits 4-7: 7:4 Command FSM states */
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#define MCI_STATUS_FSMSTATE_MASK (15 << MCI_STATUS_FSMSTATE_SHIFT)
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# define MCI_STATUS_FSMSTATE_IDLE (0 << MCI_STATUS_FSMSTATE_SHIFT) /* Idle */
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# define MCI_STATUS_FSMSTATE_INIT (1 << MCI_STATUS_FSMSTATE_SHIFT) /* Send init sequence */
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# define MCI_STATUS_FSMSTATE_TXSTART (2 << MCI_STATUS_FSMSTATE_SHIFT) /* Tx cmd start bit */
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# define MCI_STATUS_FSMSTATE_TXTXBIT (3 << MCI_STATUS_FSMSTATE_SHIFT) /* Tx cmd tx bit */
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# define MCI_STATUS_FSMSTATE_TXCMDARG (4 << MCI_STATUS_FSMSTATE_SHIFT) /* Tx cmd index + arg */
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# define MCI_STATUS_FSMSTATE_TXCMDCRC (5 << MCI_STATUS_FSMSTATE_SHIFT) /* Tx cmd crc7 */
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# define MCI_STATUS_FSMSTATE_TXEND (6 << MCI_STATUS_FSMSTATE_SHIFT) /* Tx cmd end bit */
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# define MCI_STATUS_FSMSTATE_RXSTART (7 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp start bit */
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# define MCI_STATUS_FSMSTATE_RXIRQ (8 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp IRQ response */
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# define MCI_STATUS_FSMSTATE_RXTXBIT (9 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp tx bit */
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# define MCI_STATUS_FSMSTATE_RXCMD (10 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp cmd idx */
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# define MCI_STATUS_FSMSTATE_RXRESP (11 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp data */
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# define MCI_STATUS_FSMSTATE_RXRESPCRC (12 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp crc7 */
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# define MCI_STATUS_FSMSTATE_RXEND (13 << MCI_STATUS_FSMSTATE_SHIFT) /* Rx resp end bit */
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# define MCI_STATUS_FSMSTATE_WAITNCC (14 << MCI_STATUS_FSMSTATE_SHIFT) /* Cmd path wait NCC */
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# define MCI_STATUS_FSMSTATE_WAITTURN (15 << MCI_STATUS_FSMSTATE_SHIFT) /* Wait; CMD-to-response turnaround */
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#define MCI_STATUS_FIFOFULL (1 << 3) /* Bit 3: FIFO is full */
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#define MCI_STATUS_FIFOEMPTY (1 << 2) /* Bit 2: FIFO is empty */
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#define MCI_STATUS_TXWMARK (1 << 1) /* Bit 1: FIFO reached Transmit watermark level */
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#define MCI_STATUS_RXWMARK (1 << 0) /* Bit 0: FIFO reached Receive watermark level */
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/* FIFO threshold register FIFOTH, address 0x1800004c */
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#define MCI_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */
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#define MCI_FIFOTH_DMABURST_MASK (7 << MCI_FIFOTH_DMABURST_SHIFT)
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define MCI_FIFOTH_DMABURST_1XFR (0 << MCI_FIFOTH_DMABURST_SHIFT) /* 1 transfer */
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# define MCI_FIFOTH_DMABURST_4XFRS (1 << MCI_FIFOTH_DMABURST_SHIFT) /* 4 transfers */
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# define MCI_FIFOTH_DMABURST_8XFRS (2 << MCI_FIFOTH_DMABURST_SHIFT) /* 8 transfers */
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#define MCI_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */
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#define MCI_FIFOTH_RXWMARK_MASK (0xfff << MCI_FIFOTH_RXWMARK_SHIFT)
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#define MCI_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */
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#define MCI_FIFOTH_TXWMARK_MASK (0xfff << MCI_FIFOTH_TXWMARK_SHIFT)
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/* Card detect register CDETECT, address 0x18000050 */
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#define MCI_CDETECT_NOTPRESENT (1 << 0)
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/* Write protect register WRTPRT, address 0x18000054 */
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#define MCI_WRTPRT_PROTECTED (1 << 0)
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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/************************************************************************************************
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* Public Data
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************************************************************************************************/
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/************************************************************************************************
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* Public Functions
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************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H */
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