469 lines
22 KiB
C
469 lines
22 KiB
C
/****************************************************************************
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* boards/arm/samd5e5/metro-m4/include/board.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMD5E5_METRO_M4_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMD5E5_METRO_M4_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef TRUE
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# define TRUE 1
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#endif
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#ifndef FALSE
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# define FALSE 0
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#endif
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/* Clocking *****************************************************************/
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/* Overview
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*
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* Per the schematic Adafruit Metro M4 Pro has one on-board crystal:
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*
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* X4 32.768KHz XOSC32
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*
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* However, I have been unsuccessful using it and have fallen back to using
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* OSCULP32K(Unless CONFIG_METRO_M4_32KHZXTAL=y)
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*
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* Since there is no high speed crystal, we will run from the OSC16M clock
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* source.
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*
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* OSC48M Output = 48Mhz
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* |
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* FDLL Input = 48MHz
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* | Output = 48MHz
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* GCLK5 Input = 48MHz
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* | Output = 2MHz
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* DPLL0 Input = 2MHz
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* | Output = 120MHz
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* GCLK0 Input = 120MHz
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* | Output = 120MHz
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* MCK Input = 120MHz
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* | Output = 120MHz
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* CPU Input = 120MHz
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*/
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#define BOARD_OSC32K_FREQUENCY 32768 /* OSCULP32K frequency 32.768 KHz (nominal) */
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#define BOARD_XOSC32K_FREQUENCY 32768 /* XOSC32K frequency 32.768 KHz */
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#define BOARD_DFLL_FREQUENCY 48000000 /* FDLL frequency 28MHz */
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#define BOARD_XOSC0_FREQUENCY 12000000 /* XOSC0 frequency 12MHz (disabled) */
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#define BOARD_XOSC1_FREQUENCY 12000000 /* XOSC0 frequency 12MHz (disabled)*/
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#define BOARD_DPLL0_FREQUENCY 120000000 /* DPLL0 output frueuency (120MHz) */
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#define BOARD_DPLL1_FREQUENCY 47985664 /* DPLL1 output frequency (disabled) */
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#define BOARD_GCLK0_FREQUENCY BOARD_DPLL0_FREQUENCY
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#define BOARD_GCLK1_FREQUENCY BOARD_DFLL_FREQUENCY
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#define BOARD_GCLK2_FREQUENCY (BOARD_XOSC32K_FREQUENCY / 4) /* Disabled */
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#ifdef CONFIG_METRO_M4_32KHZXTAL
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# define BOARD_GCLK3_FREQUENCY BOARD_XOSC32K_FREQUENCY /* Enabled */
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#else
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# define BOARD_GCLK3_FREQUENCY BOARD_OSC32K_FREQUENCY /* Always-on */
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#endif
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#define BOARD_GCLK4_FREQUENCY BOARD_DPLL0_FREQUENCY
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#define BOARD_GCLK5_FREQUENCY (BOARD_DFLL_FREQUENCY / 24)
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#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK7_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK8_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK9_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK10_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_CPU_FREQUENCY BOARD_GCLK0_FREQUENCY /* CPU frequency 120MHz */
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/* XOSC32 */
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#ifdef CONFIG_METRO_M4_32KHZXTAL
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# define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
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# define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
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#else
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# define BOARD_HAVE_XOSC32K 0 /* No 32.768 KHz XOSC32 crystal installed */
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# define BOARD_XOSC32K_ENABLE FALSE /* Disable XOSC32 */
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#endif
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#define BOARD_XOSC32K_XTALEN TRUE /* Crystal connected on XIN32 */
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#define BOARD_XOSC32K_EN32K FALSE /* No 32KHz output */
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#define BOARD_XOSC32K_EN1K FALSE /* No 1KHz output */
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#define BOARD_XOSC32K_HIGHSPEED TRUE /* High speed mode */
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#define BOARD_XOSC32K_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC32K_ONDEMAND TRUE /* Enable on-demand control */
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#define BOARD_XOSC32K_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC32K_CFDEO FALSE /* No clock failure event */
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#define BOARD_XOSC32K_CALIBEN FALSE /* No OSCULP32K calibration */
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#define BOARD_XOSC32K_STARTUP 0 /* Startup time: 62592us */
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#define BOARD_XOSC32K_CALIB 0 /* Dummy OSCULP32K calibration value */
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#define BOARD_XOSC32K_RTCSEL 0 /* RTC clock = ULP1K */
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/* XOSC0 */
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#define BOARD_HAVE_XOSC0 0 /* No XOSC0 clock/crystal installed */
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#define BOARD_XOSC0_ENABLE FALSE /* Don't enable XOSC0 */
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#define BOARD_XOSC0_XTALEN FALSE /* External clock connected */
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#define BOARD_XOSC0_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC0_ONDEMAND TRUE /* Disable on-demand control */
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#define BOARD_XOSC0_LOWGAIN FALSE /* Disable low buffer gain */
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#define BOARD_XOSC0_ENALC FALSE /* Disable automatic loop control */
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#define BOARD_XOSC0_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC0_SWBEN FALSE /* XOSC clock switch not enabled */
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#define BOARD_XOSC0_STARTUP 0 /* XOSC0 start-up time 31µs */
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/* XOSC1 */
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#define BOARD_HAVE_XOSC1 0 /* No XOSC0 clock/crystal installed */
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#define BOARD_XOSC1_ENABLE FALSE /* Don't enable XOSC1 */
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#define BOARD_XOSC1_XTALEN TRUE /* External crystal connected */
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#define BOARD_XOSC1_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC1_ONDEMAND TRUE /* Disable on-demand control */
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#define BOARD_XOSC1_LOWGAIN FALSE /* Disable low buffer gain */
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#define BOARD_XOSC1_ENALC FALSE /* Disable automatic loop control */
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#define BOARD_XOSC1_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC1_SWBEN FALSE /* XOSC clock switch not enabled */
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#define BOARD_XOSC1_STARTUP 0 /* XOSC0 start-up time 31µs */
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/* GCLK */
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#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */
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#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
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#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
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#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
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#define BOARD_GCLK0_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */
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#define BOARD_GCLK0_DIV 1 /* Division factor */
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#define BOARD_GCLK1_ENABLE TRUE /* Enable GCLK1 */
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#define BOARD_GCLK1_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK1_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK1_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
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#define BOARD_GCLK1_DIV 1 /* Division factor */
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#define BOARD_GCLK2_ENABLE FALSE /* Don't enable GCLK2 */
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#define BOARD_GCLK2_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK2_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK2_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK2_SOURCE 1 /* Select XOSC1 as GCLK2 source */
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#define BOARD_GCLK2_DIV 1 /* Division factor */
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#define BOARD_GCLK3_ENABLE TRUE /* Enable GCLK3 */
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#define BOARD_GCLK3_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK3_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK3_RUNSTDBY FALSE /* Don't run in standby */
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#ifdef CONFIG_METRO_M4_32KHZXTAL
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# define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
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#else
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# define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
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#endif
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#define BOARD_GCLK3_DIV 1 /* Division factor */
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#define BOARD_GCLK4_ENABLE TRUE /* Enable GCLK4 */
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#define BOARD_GCLK4_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK4_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK4_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
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#define BOARD_GCLK4_DIV 1 /* Division factor */
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#define BOARD_GCLK5_ENABLE TRUE /* Enable GCLK5 */
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#define BOARD_GCLK5_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK5_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK5_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
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#define BOARD_GCLK5_DIV 24 /* Division factor */
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#define BOARD_GCLK6_ENABLE FALSE /* Don't enable GCLK6 */
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#define BOARD_GCLK6_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK6_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK6_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
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#define BOARD_GCLK6_DIV 1 /* Division factor */
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#define BOARD_GCLK7_ENABLE FALSE /* Don't enable GCLK7 */
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#define BOARD_GCLK7_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK7_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK7_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
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#define BOARD_GCLK7_DIV 1 /* Division factor */
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#define BOARD_GCLK8_ENABLE FALSE /* Don't enable GCLK8 */
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#define BOARD_GCLK8_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK8_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK8_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
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#define BOARD_GCLK8_DIV 1 /* Division factor */
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#define BOARD_GCLK9_ENABLE FALSE /* Don't enable GCLK9 */
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#define BOARD_GCLK9_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK9_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK9_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
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#define BOARD_GCLK9_DIV 1 /* Division factor */
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#define BOARD_GCLK10_ENABLE FALSE /* Don't enable GCLK10 */
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#define BOARD_GCLK10_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK10_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK10_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
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#define BOARD_GCLK10_DIV 1 /* Division factor */
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#define BOARD_GCLK11_ENABLE FALSE /* Don't enable GCLK11 */
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#define BOARD_GCLK11_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK11_OE FALSE /* No generator output of GCLK_IO */
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#define BOARD_GCLK11_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
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#define BOARD_GCLK11_DIV 1 /* Division factor */
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#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
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/* FDLL */
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#define BOARD_DFLL_ENABLE TRUE /* DFLL enable */
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#define BOARD_DFLL_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_DFLL_ONDEMAND FALSE /* No n-demand control */
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#define BOARD_DFLL_MODE FALSE /* Open loop mode */
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#define BOARD_DFLL_STABLE FALSE /* No stable DFLL frequency */
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#define BOARD_DFLL_LLAW FALSE /* Don't ose lock after wake */
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#define BOARD_DFLL_USBCRM TRUE /* Use USB clock recovery mode */
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#define BOARD_DFLL_CCDIS TRUE /* Chill cycle disable */
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#define BOARD_DFLL_QLDIS FALSE /* No Quick Lock Disable */
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#define BOARD_DFLL_BPLCKC FALSE /* No ypass coarse clock */
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#define BOARD_DFLL_WAITLOCK TRUE /* Wait lock */
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#define BOARD_DFLL_CALIBEN FALSE /* Don't verwrite factory calibration */
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#define BOARD_DFLL_GCLKLOCK FALSE /* Don't lock the GCLK source */
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#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */
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#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */
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#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */
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#define BOARD_DFLL_CSTEP 1 /* Coarse maximum step */
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#define BOARD_DFLL_GCLK 3 /* GCLK source (if !usbcrm && !mode) */
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#define BOARD_DFLL_MUL 0 /* DFLL multiply factor */
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/* DPLL0/1
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*
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* Fckr is the frequency of the selected reference clock reference:
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*
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* BOARD_XOSC32K_FREQENCY,
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* BOARD_XOSCn_FREQUENCY / DIV, or
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* BOARD_GCLKn_FREQUENCY
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*
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* The DPLL output frequency is then given by:
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*
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* Fdpll = Fckr * (LDR + 1 + LDRFRAC / 32)
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*
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* DPLL0:
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* Fckr = BOARD_GCLK5_FREQUENCY = BOARD_DFLL_FREQUENCY / 24 = 2MHz
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* Fdpll = 2Mhz * (59 + 1 + 0 / 32) = 120MHz
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*
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* DPLL1: (not enabled)
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* Fckr = BOARD_XOSCK32_FREQUENCY = 32.768KHz
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* Fdpll = 32768 * (1463 + 1 + 13/32) = 47.986 MHz
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*/
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#define BOARD_DPLL0_ENABLE TRUE /* DPLL enable */
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#define BOARD_DPLL0_DCOEN FALSE /* DCO filter enable */
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#define BOARD_DPLL0_LBYPASS FALSE /* Lock bypass */
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#define BOARD_DPLL0_WUF FALSE /* Wake up fast */
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#define BOARD_DPLL0_RUNSTDBY FALSE /* Run in standby */
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#define BOARD_DPLL0_ONDEMAND FALSE /* On demand clock activation */
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#define BOARD_DPLL0_REFLOCK FALSE /* Do not lock reference clock section */
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#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */
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#define BOARD_DPLL0_LTIME 0 /* Lock time */
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#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */
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#define BOARD_DPLL0_DCOFILTER 0 /* Sigma-delta DCO filter selection */
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#define BOARD_DPLL0_GCLK 5 /* GCLK source (if refclock == 0) */
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#define BOARD_DPLL0_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
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#define BOARD_DPLL0_LDRFRAC 0 /* Loop divider fractional part */
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#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */
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#define BOARD_DPLL0_DIV 0 /* Clock divider */
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#define BOARD_DPLL1_ENABLE FALSE /* DPLL enable */
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#define BOARD_DPLL1_DCOEN FALSE /* DCO filter enable */
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#define BOARD_DPLL1_LBYPASS FALSE /* Lock bypass */
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#define BOARD_DPLL1_WUF FALSE /* Wake up fast */
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#define BOARD_DPLL1_RUNSTDBY FALSE /* Run in standby */
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#define BOARD_DPLL1_ONDEMAND FALSE /* On demand clock activation */
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#define BOARD_DPLL1_REFLOCK FALSE /* Do not lock reference clock section */
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#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */
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#define BOARD_DPLL1_LTIME 0 /* Lock time */
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#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */
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#define BOARD_DPLL1_DCOFILTER 0 /* Sigma-delta DCO filter selection */
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#define BOARD_DPLL1_GCLK 0 /* GCLK source (if refclock == 0) */
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#define BOARD_DPLL1_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
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#define BOARD_DPLL1_LDRFRAC 13 /* Loop divider fractional part */
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#define BOARD_DPLL1_LDRINT 1463 /* Loop divider ratio */
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#define BOARD_DPLL1_DIV 0 /* Clock divider */
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/* Master Clock (MCLK)
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*
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* GCLK0 is always the direct source the GCLK_MAIN.
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* CPU frequency = 120MHz / 1 = 120MHz
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*/
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#define BOARD_MCLK_CPUDIV 1 /* MCLK divider to get CPU frequency */
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/* Peripheral clocking */
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#define BOARD_GCLK_EIC 4 /* EIC GCLK index */
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/* FLASH wait states
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*
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* Vdd Range Wait states Maximum Operating Frequency
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* --------- ----------- ---------------------------
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* > 2.7V 0 24 MHz
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* 1 51 MHz
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* 2 77 MHz
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* 3 101 MHz
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* 4 119 MHz
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* 5 120 MHz
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* >1.71V 0 22 MHz
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* 1 44 MHz
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* 2 67 MHz
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* 3 89 MHz
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* 4 111 MHz
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* 5 120 MHz
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*/
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#define BOARD_FLASH_WAITSTATES 6
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/* LED definitions **********************************************************/
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/* The Adafruit Metro M4 has four LEDs, but only two are controllable by
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* software:
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*
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* 1. The red LED on the Arduino D13 pin, and
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* 2. A NeoPixel RGB LED.
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*
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* Currently, only the red LED is supported.
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*
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* ------ ----------------- -----------
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* SHIELD SAMD5E5 FUNCTION
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* ------ ----------------- -----------
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* D13 PA16 GPIO output
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_RED_LED 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_RED_LED_BIT (1 << BOARD_RED_LED)
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/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_autoleds.c. The LEDs are used to encode
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* OS-related events as follows:
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*
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* ------------------- ---------------------------- ------
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* SYMBOL Meaning LED
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* ------------------- ---------------------------- ------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON */
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#define LED_INIRQ 2 /* In an interrupt N/C */
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#define LED_SIGNAL 2 /* In a signal handler N/C */
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#define LED_ASSERTION 2 /* An assertion failed N/C */
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#define LED_PANIC 3 /* The system has crashed FLASH */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* Thus is LED is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If LED is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*/
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/* Alternate function pin selections ****************************************/
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/* SERCOM definitions *******************************************************/
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/* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the
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* Main Clock Controller.
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* The SERCOM uses two generic clocks: GCLK_SERCOMn_CORE and GCLK_SERCOM_SLOW.
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* The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while
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* working as a master. The slow clock (GCLK_SERCOM_SLOW) is only required
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* for certain functions and is common to all SERCOM modules.
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*
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* These clocks must be configured and enabled in the Generic Clock
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* Controller (GCLK) before using the SERCOM.
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*/
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#define BOARD_SERCOM_SLOWGEN 3 /* 32.768KHz, common to all SERCOMS */
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#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
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#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY
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/* SERCOM3
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*
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* An Arduino compatible serial Shield is assumed (or equivalently, an
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* external RS-232 or serial-to-USB adapter connected on Arduino pins D0
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* and D1):
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*
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* ------ ----------------- ---------
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* SHIELD SAMD5E5 FUNCTION
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* ------ ----------------- ---------
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* D0 PA23 SERCOM3 PAD1 RXD
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* D1 PA22 SERCOM3 PAD0 TXD
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*
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* NOTES:
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* USART_CTRLA_TXPAD0_2: TxD=PAD0 XCK=N/A RTS/TE=PAD2 CTS=PAD3
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* USART_CTRLA_RXPAD1: RxD=PAD1
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*/
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#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD1)
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#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* PAD0: USART TX */
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#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* PAD1: USART RX */
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#define BOARD_SERCOM3_PINMAP_PAD2 0 /* PAD2: (not used) */
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#define BOARD_SERCOM3_PINMAP_PAD3 0 /* PAD3: (not used) */
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#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* INTFLAG[0] DRE */
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#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2 /* INTFLAG[2] RXC */
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#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
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#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
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#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK1_FREQUENCY
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/* USB */
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#define BOARD_USB_GCLKGEN 1 /* GCLK1, 48MHz */
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#endif /* __BOARDS_ARM_SAMD5E5_METRO_M4_INCLUDE_BOARD_H */
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