476 lines
21 KiB
C
476 lines
21 KiB
C
/****************************************************************************************************
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* configs/shenzhou/src/shenzhou.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __CONFIGS_SHENZHOUL_SRC_SHENZHOU_H
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#define __CONFIGS_SHENZHOUL_SRC_SHENZHOU_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <stdint.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Configuration ************************************************************************************/
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/* How many SPI modules does this chip support? */
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#if STM32_NSPI < 1
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# undef CONFIG_STM32_SPI1
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# undef CONFIG_STM32_SPI2
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# undef CONFIG_STM32_SPI3
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#elif STM32_NSPI < 2
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# undef CONFIG_STM32_SPI2
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# undef CONFIG_STM32_SPI3
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#elif STM32_NSPI < 3
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# undef CONFIG_STM32_SPI3
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#endif
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/* Shenzhou GPIO Configuration **********************************************************************/
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/* STM3240G-EVAL GPIOs ******************************************************************************/
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/* Ethernet
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*
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* -- ---- -------------- ----------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- ----------------------------------------------------------
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* 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of these
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* RMII_REF_CLK Ethernet PHY signals, the DM916AEP is actually configured
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* 25 PA2 MII_MDIO Ethernet PHY to work in RMII mode.
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* 48 PB11 MII_TX_EN Ethernet PHY
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* 51 PB12 MII_TXD0 Ethernet PHY
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* 52 PB13 MII_TXD1 Ethernet PHY
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* 16 PC1 MII_MDC Ethernet PHY
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* 34 PC5 MII_INT Ethernet PHY
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* 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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*
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* The board desdign can support a 50MHz external clock to drive the PHY
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* (U9). However, on my board, U9 is not present.
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*
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* 67 PA8 MCO DM9161AEP
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*/
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#ifdef CONFIG_STM32_ETHMAC
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# define GPIO_MII_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN5)
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#endif
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/* Wireless
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 26 PA3 315M_VT
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* 17 PC2 WIRELESS_INT
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* 18 PC3 WIRELESS_CE To the NRF24L01 2.4G wireless module
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* 59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
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*/
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#define GPIO_WIRELESS_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN12)
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/* Buttons
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 23 PA0 WAKEUP Connected to KEY4. Active low: Closing KEY4 pulls WAKEUP to ground.
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* 47 PB10 USERKEY Connected to KEY2
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* 33 PC4 USERKEY2 Connected to KEY1
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* 7 PC13 TAMPER Connected to KEY3
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*/
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/* BUTTONS -- NOTE that all have EXTI interrupts configured */
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#define MIN_IRQBUTTON BUTTON_KEY1
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#define MAX_IRQBUTTON BUTTON_KEY4
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#define NUM_IRQBUTTONS (BUTTON_KEY4 - BUTTON_KEY1 + 1)
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#define GPIO_BTN_WAKEUP (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_BTN_USERKEY (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_BTN_USERKEY2 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_BTN_TAMPER (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
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/* LEDs
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 83 PD2 LED1 Active low: Pulled high
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* 84 PD3 LED2 Active low: Pulled high
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* 85 PD4 LED3 Active low: Pulled high
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* 88 PD7 LED4 Active low: Pulled high
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*/
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#define GPIO_LED1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN2)
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#define GPIO_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN3)
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#define GPIO_LED3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN4)
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#define GPIO_LED4 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN7)
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/* TFT LCD
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 37 PB2 DATA_LE To TFT LCD. (CN13, ping 28)
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* 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and to the W25X16 SPI FLASH
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* 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26)
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* 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19)
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* 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31)
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* 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29)
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* 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25)
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* 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27)
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* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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* 60 PD13 LCD_RS To TFT LCD (CN13, pin 20)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
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* 62 PD15 LCD_RD To TFT LCD (CN13, pin 22)
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* 97 PE0 DB00 To TFT LCD (CN13, pin 3)
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* 98 PE1 DB01 To TFT LCD (CN13, pin 4)
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* 1 PE2 DB02 To TFT LCD (CN13, pin 5)
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* 2 PE3 DB03 To TFT LCD (CN13, pin 6)
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* 3 PE4 DB04 To TFT LCD (CN13, pin 7)
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* 4 PE5 DB05 To TFT LCD (CN13, pin 8)
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* 5 PE6 DB06 To TFT LCD (CN13, pin 9)
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* 38 PE7 DB07 To TFT LCD (CN13, pin 10)
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* 39 PE8 DB08 To TFT LCD (CN13, pin 11)
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* 40 PE9 DB09 To TFT LCD (CN13, pin 12)
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* 41 PE10 DB10 To TFT LCD (CN13, pin 13)
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* 42 PE11 DB11 To TFT LCD (CN13, pin 16)
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* 43 PE12 DB12 To TFT LCD (CN13, pin 15)
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* 44 PE13 DB13 To TFT LCD (CN13, pin 16)
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* 45 PE14 DB14 To TFT LCD (CN13, pin 17)
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* 46 PE15 DB15 To TFT LCD (CN13, pin 18)
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*
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* NOTE: The backlight signl NC_BL (CN13, pin 24) is pulled high and not under
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* software control
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*
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* On LCD module:
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* -- -------------- -------------------------------------------------------------------
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* PN SIGNAL NOTES
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* -- -------------- -------------------------------------------------------------------
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* 3 DB01 To LCD DB1
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* 4 DB00 To LCD DB0
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* 5 DB03 To LCD DB3
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* 6 DB02 To LCD DB2
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* 7 DB05 To LCD DB5
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* 8 DB04 To LCD DB4
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* 9 DB07 To LCD DB7
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* 10 DB06 To LCD DB6
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* 11 DB09 To LCD DB9
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* 12 DB08 To LCD DB8
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* 13 DB11 To LCD DB11
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* 14 DB10 To LCD DB10
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* 15 DB13 To LCD DB13
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* 16 DB12 To LCD DB12
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* 17 DB15 To LCD DB15
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* 18 DB14 To LCD DB14
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* 19 RS To LCD RS
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* 20 /LCD_CS To LCD CS
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* 21 /RD To LCD RD
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* 22 /WR To LCD WR
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* 23 BL_EN (Not referenced)
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* 24 /RESET
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* 25 /INT To Touch IC /INT
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* 26 MISO To Touch IC DOUT; To AT45DB161B SO; To SD card DAT0
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* 27 LE To 74HC573 that controls LCD 8-bit/16-bit mode
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* 28 MOSI To Touch IC DIN; To AT45DB161B SI; To SD card CMD
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* 29 /DF_CS To AT45DB161B Data Flash /CS
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* 30 SCLK To Touch IC DCLK; To AT45DB161B SCK; To SD card CLK
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* 31 /SD_CS To SD card /CS
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* 31 /TP_CS To Touch IC CS
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*/
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/* TFT LCD GPIOs */
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#define GPIO_LCD_D0OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN0)
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#define GPIO_LCD_D1OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN1)
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#define GPIO_LCD_D2OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_LCD_D3OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
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#define GPIO_LCD_D4OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
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#define GPIO_LCD_D5OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN5)
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#define GPIO_LCD_D6OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN6)
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#define GPIO_LCD_D7OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN7)
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#define GPIO_LCD_D8OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN8)
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#define GPIO_LCD_D9OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN9)
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#define GPIO_LCD_D10OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN10)
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#define GPIO_LCD_D11OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN11)
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#define GPIO_LCD_D12OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN12)
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#define GPIO_LCD_D13OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN13)
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#define GPIO_LCD_D14OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN14)
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#define GPIO_LCD_D15OUT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN15)
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#define GPIO_LCD_D0IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN0)
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#define GPIO_LCD_D1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN1)
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#define GPIO_LCD_D2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_LCD_D3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN3)
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#define GPIO_LCD_D4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN4)
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#define GPIO_LCD_D5IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN5)
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#define GPIO_LCD_D6IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN6)
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#define GPIO_LCD_D7IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN7)
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#define GPIO_LCD_D8IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN8)
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#define GPIO_LCD_D9IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN9)
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#define GPIO_LCD_D10IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN10)
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#define GPIO_LCD_D11IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN11)
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#define GPIO_LCD_D12IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN12)
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#define GPIO_LCD_D13IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN13)
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#define GPIO_LCD_D14IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN14)
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#define GPIO_LCD_D15IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTE|GPIO_PIN15)
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#define GPIO_LCD_RS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN13)
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#define GPIO_LCD_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN8)
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#define GPIO_LCD_RD (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN15)
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#define GPIO_LCD_WR (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN14)
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#define GPIO_LCD_LE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN2)
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/* Bit band addresses */
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#define STM32_GPIOB_OFFSET (STM32_GPIOB_BASE - STM32_PERIPH_BASE)
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#define STM32_GPIOC_OFFSET (STM32_GPIOC_BASE - STM32_PERIPH_BASE)
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#define STM32_GPIOD_OFFSET (STM32_GPIOD_BASE - STM32_PERIPH_BASE)
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#define LCD_BIT_CLEAR(offs,pin) \
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(STM32_PERIPHBB_BASE + ((offs + STM32_GPIO_BRR_OFFSET) << 5) + ((pin) << 2))
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#define LCD_BIT_SET(offs,pin) \
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(STM32_PERIPHBB_BASE + ((offs + STM32_GPIO_BSRR_OFFSET) << 5) + ((pin) << 2))
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#define LCD_BIT_READ(offs,pin) \
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(STM32_PERIPHBB_BASE + ((offs + STM32_GPIO_ODR_OFFSET) << 5) + ((pin) << 2))
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#define LCD_RS_CLEAR LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 13) /* GPIO_PORTD|GPIO_PIN13 */
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#define LCD_RS_SET LCD_BIT_SET(STM32_GPIOD_OFFSET, 13)
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#define LCD_RS_READ LCD_BIT_READ(STM32_GPIOD_OFFSET, 13)
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#define LCD_CS_CLEAR LCD_BIT_CLEAR(STM32_GPIOC_OFFSET, 8) /* GPIO_PORTC|GPIO_PIN8 */
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#define LCD_CS_SET LCD_BIT_SET(STM32_GPIOC_OFFSET, 8)
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#define LCD_CS_READ LCD_BIT_READ(STM32_GPIOC_OFFSET, 8)
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#define LCD_RD_CLEAR LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 15) /* GPIO_PORTD|GPIO_PIN15 */
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#define LCD_RD_SET LCD_BIT_SET(STM32_GPIOD_OFFSET, 15)
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#define LCD_RD_READ LCD_BIT_READ(STM32_GPIOD_OFFSET, 15)
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#define LCD_WR_CLEAR LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 14) /* GPIO_PORTB|GPIO_PIN14 */
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#define LCD_WR_SET LCD_BIT_SET(STM32_GPIOB_OFFSET, 14)
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#define LCD_WR_READ LCD_BIT_READ(STM32_GPIOB_OFFSET, 14)
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#define LCD_LE_CLEAR LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 2) /* GPIO_PORTB|GPIO_PIN2 */
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#define LCD_LE_SET LCD_BIT_SET(STM32_GPIOB_OFFSET, 2)
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#define LCD_LE_READ LCD_BIT_READ(STM32_GPIOB_OFFSET, 2)
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#define LCD_CRL STM32_GPIOE_CRL
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#define LCD_CRH STM32_GPIOE_CRH
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#define LCD_INPUT 0x44444444 /* Floating input */
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#define LCD_OUTPUT 0x33333333 /* Push/pull output */
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#define LCD_ODR STM32_GPIOE_ODR
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#define LCD_IDR STM32_GPIOE_IDR
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/* Touchscreen IC on the LCD module */
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#define GPIO_TP_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_TP_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN9)
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/* AT45DB161B Data Flash on the LCD module */
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#define GPIO_LCDDF_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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/* SD card on the LCD module */
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#define GPIO_LCDSD_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN11)
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/* RS-485
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 88 PD7 485_DIR SP3485 read enable (not)
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*/
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/* To be provided */
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/* USB
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 95 PB8 USB_PWR Drives USB VBUS
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*/
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#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_SPEED_100MHz|\
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GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
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/* Audio DAC
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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*/
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/* To be provided */
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/* SPI FLASH
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 96 PB9 F_CS To both the TFT LCD (CN13) and to the W25X16 SPI FLASH
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*/
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#define GPIO_FLASH_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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/* SD Card
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 53 PB14 SD_CD Active low: Pulled high. Schematic is wrong LCD_WR is PB14.
|
|
* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
|
|
*/
|
|
|
|
#define GPIO_SD_CD (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN14)
|
|
#define GPIO_SD_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
|
|
GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN11)
|
|
|
|
/* Relays */
|
|
|
|
#define NUM_RELAYS 2
|
|
#define GPIO_RELAYS_R00 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
|
|
GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN0)
|
|
#define GPIO_RELAYS_R01 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
|
|
GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN1)
|
|
|
|
/****************************************************************************************************
|
|
* Public Types
|
|
****************************************************************************************************/
|
|
|
|
/****************************************************************************************************
|
|
* Public data
|
|
****************************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/****************************************************************************************************
|
|
* Public Functions
|
|
****************************************************************************************************/
|
|
|
|
/****************************************************************************************************
|
|
* Name: stm32_spidev_initialize
|
|
*
|
|
* Description:
|
|
* Called to configure SPI chip select GPIO pins for the STM3240G-EVAL board.
|
|
*
|
|
****************************************************************************************************/
|
|
|
|
void weak_function stm32_spidev_initialize(void);
|
|
|
|
/****************************************************************************************************
|
|
* Name: stm32_usbinitialize
|
|
*
|
|
* Description:
|
|
* Called from stm32_usbinitialize very early in inialization to setup USB-related GPIO pins for
|
|
* the STM3240G-EVAL board.
|
|
*
|
|
****************************************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_OTGFS
|
|
void weak_function stm32_usbinitialize(void);
|
|
#endif
|
|
|
|
/****************************************************************************************************
|
|
* Name: stm32_usbhost_initialize
|
|
*
|
|
* Description:
|
|
* Called at application startup time to initialize the USB host functionality. This function will
|
|
* start a thread that will monitor for device connection/disconnection events.
|
|
*
|
|
****************************************************************************************************/
|
|
|
|
#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST)
|
|
int stm32_usbhost_initialize(void);
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_sdinitialize
|
|
*
|
|
* Description:
|
|
* Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n
|
|
* and CONFIG_STM32_SPI1=y
|
|
*
|
|
****************************************************************************/
|
|
|
|
int stm32_sdinitialize(int minor);
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_w25initialize
|
|
*
|
|
* Description:
|
|
* Initialize and register the W25 FLASH file system.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_MTD_W25
|
|
int stm32_w25initialize(int minor);
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __CONFIGS_SHENZHOUL_SRC_SHENZHOU_H */
|