245 lines
7.7 KiB
C
245 lines
7.7 KiB
C
/****************************************************************************
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* arch/arm/src/c5471/c5471_irq.c
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*
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* Copyright (C) 2007, 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/irq.h>
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#include "arm.h"
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#include "chip.h"
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define ILR_EDGESENSITIVE 0x00000020
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#define ILR_PRIORITY 0x0000001E
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/****************************************************************************
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* Public Data
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****************************************************************************/
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volatile uint32_t *current_regs;
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* The value of _svectors is defined in ld.script. It could be hard-coded
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* because we know that correct IRAM area is 0xffc00000.
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*/
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extern int _svectors; /* Type does not matter */
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/* The C5471 has FLASH at the low end of memory. The rrload bootloaer will
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* catch all interrupts and re-vector them to vectors stored in IRAM. The
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* following table is used to initialize those vectors.
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*/
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static up_vector_t g_vectorinittab[] =
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{
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(up_vector_t)NULL,
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up_vectorundefinsn,
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up_vectorswi,
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up_vectorprefetch,
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up_vectordata,
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up_vectoraddrexcptn,
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up_vectorirq,
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up_vectorfiq
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};
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#define NVECTORS ((sizeof(g_vectorinittab)) / sizeof(up_vector_t))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_ackirq
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*
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* Description:
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* Acknowlede the IRQ.Bit 0 of the Interrupt Control
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* Register == New IRQ agreement (NEW_IRQ_AGR). Reset IRQ
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* output. Clear source IRQ register. Enables a new IRQ
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* generation. Reset by internal logic.
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*
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****************************************************************************/
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static inline void up_ackirq(unsigned int irq)
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{
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uint32_t reg;
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reg = getreg32(SRC_IRQ_REG); /* Insure appropriate IT_REG bit clears */
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putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */
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}
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/****************************************************************************
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* Name: up_ackfiq
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*
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* Description:
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* Acknowledge the FIQ. Bit 1 of the Interrupt Control
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* Register == New FIQ agreement (NEW_FIQ_AGR). Reset FIQ
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* output. Clear source FIQ register. Enables a new FIQ
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* generation. Reset by internal logic.
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*
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****************************************************************************/
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static inline void up_ackfiq(unsigned int irq)
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{
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uint32_t reg;
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reg = getreg32(SRC_FIQ_REG); /* Insure appropriate IT_REG bit clears */
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putreg32(reg | 0x00000002, INT_CTRL_REG); /* write the NEW_FIQ_AGR bit. */
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}
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/****************************************************************************
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* Name: up_vectorinitialize
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****************************************************************************/
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static inline void up_vectorinitialize(void)
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{
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up_vector_t *src = g_vectorinittab;
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up_vector_t *dest = (up_vector_t*)&_svectors;
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int i;
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for (i = 0; i < NVECTORS; i++)
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{
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*dest++ = *src++;
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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/* Disable all interrupts. */
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putreg32(0x0000ffff, MASK_IT_REG);
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/* Clear any pending interrupts */
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up_ackirq(0);
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up_ackfiq(0);
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putreg32(0x00000000, IT_REG);
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/* Override hardware defaults */
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putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ2_REG);
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putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ4_REG);
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putreg32(ILR_PRIORITY, ILR_IRQ6_REG);
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putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ15_REG);
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/* Initialize hardware interrupt vectors */
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up_vectorinitialize();
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current_regs = NULL;
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/* And finally, enable interrupts */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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irqrestore(SVC_MODE | PSR_F_BIT);
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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uint32_t reg = getreg32(MASK_IT_REG);
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putreg32(reg | (1 << irq), MASK_IT_REG);
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}
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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if ((unsigned)irq < NR_IRQS)
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{
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uint32_t reg = getreg32(MASK_IT_REG);
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putreg32(reg & ~(1 << irq), MASK_IT_REG);
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}
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}
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/****************************************************************************
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* Name: up_maskack_irq
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*
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* Description:
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* Mask the IRQ and acknowledge it
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*
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****************************************************************************/
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void up_maskack_irq(int irq)
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{
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uint32_t reg;
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/* Mask the interrupt */
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reg = getreg32(MASK_IT_REG);
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putreg32(reg | (1 << irq), MASK_IT_REG);
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/* Set the NEW_IRQ_AGR bit. This clears the IRQ src register
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* enables generation of a new IRQ.
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*/
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reg = getreg32(INT_CTRL_REG);
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putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */
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}
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