166 lines
7.8 KiB
C
166 lines
7.8 KiB
C
/************************************************************************************
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* arch/arm/src/lpc2378/lpc23xx_i2c.h
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*
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* Copyright (C) 2013 Li Zhuoyi. All rights reserved.
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* Author: Li Zhuoyi <lzyy.cn@gmail.com>
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*
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* Derived arch/arm/src/lpc17xx/lpc17_i2c.h
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*
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* Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_I2C_H
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#define __ARCH_ARM_SRC_LPC2378_LPC23XX_I2C_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* I2C Pin Configuration ************************************************************/
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#define I2C0_PCLKSEL_MASK (0x03 << 14)
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#define I2C1_PCLKSEL_MASK (0x03 << 6)
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#define I2C2_PCLKSEL_MASK (0x03 << 20)
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#define I2C0_PCLKSEL (0x01 << 14)
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#define I2C1_PCLKSEL (0x01 << 6)
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#define I2C2_PCLKSEL (0x01 << 20)
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#define I2C0_PINSEL_MASK (0x0f << 22) /* P0.27 P0.28 PINSEL1 */
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#define I2C1_PINSEL_MASK (0x0f) /* P0.0 P0.1 PINSEL0 */
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#define I2C2_PINSEL_MASK (0x0f << 22) /* P0.10 P0.11 PINSEL0 */
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#define I2C0_PINSEL (0x05 << 22)
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#define I2C1_PINSEL (0x0f)
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#define I2C2_PINSEL (0x0a << 22)
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/* I2C Register addresses ***********************************************************/
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#define I2C0_CONSET (I2C0_BASE_ADDR+I2C_CONSET_OFFSET)
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#define I2C0_STAT (I2C0_BASE_ADDR+I2C_STAT_OFFSET)
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#define I2C0_DAT (I2C0_BASE_ADDR+I2C_DAT_OFFSET)
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#define I2C0_ADR0 (I2C0_BASE_ADDR+I2C_ADR0_OFFSET)
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#define I2C0_SCLH (I2C0_BASE_ADDR+I2C_SCLH_OFFSET)
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#define I2C0_SCLL (I2C0_BASE_ADDR+I2C_SCLL_OFFSET)
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#define I2C0_CONCLR (I2C0_BASE_ADDR+I2C_CONCLR_OFFSET)
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#define I2C1_CONSET (I2C1_BASE_ADDR+I2C_CONSET_OFFSET)
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#define I2C1_STAT (I2C1_BASE_ADDR+I2C_STAT_OFFSET)
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#define I2C1_DAT (I2C1_BASE_ADDR+I2C_DAT_OFFSET)
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#define I2C1_ADR0 (I2C1_BASE_ADDR+I2C_ADR0_OFFSET)
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#define I2C1_SCLH (I2C1_BASE_ADDR+I2C_SCLH_OFFSET)
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#define I2C1_SCLL (I2C1_BASE_ADDR+I2C_SCLL_OFFSET)
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#define I2C1_CONCLR (I2C1_BASE_ADDR+I2C_CONCLR_OFFSET)
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#define I2C2_CONSET (I2C2_BASE_ADDR+I2C_CONSET_OFFSET)
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#define I2C2_STAT (I2C2_BASE_ADDR+I2C_STAT_OFFSET)
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#define I2C2_DAT (I2C2_BASE_ADDR+I2C_DAT_OFFSET)
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#define I2C2_ADR0 (I2C2_BASE_ADDR+I2C_ADR0_OFFSET)
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#define I2C2_SCLH (I2C2_BASE_ADDR+I2C_SCLH_OFFSET)
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#define I2C2_SCLL (I2C2_BASE_ADDR+I2C_SCLL_OFFSET)
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#define I2C2_CONCLR (I2C2_BASE_ADDR+I2C_CONCLR_OFFSET)
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/* I2C Register bit definitions *****************************************************/
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/* I2C Control Set Register */
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/* Bits 0-1: Reserved */
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#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
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#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
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#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
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#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
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#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
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/* Bits 7-31: Reserved */
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/* I2C Control Clear Register */
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/* Bits 0-1: Reserved */
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#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
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#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
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/* Bit 4: Reserved */
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#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
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#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
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/* Bits 7-31: Reserved */
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/* I2C Status Register
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*
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* See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January
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* 2010, NXP for definitions of status codes.
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*/
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#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
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* Bits 0-1 always zero */
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/* Bits 8-31: Reserved */
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/* I2C Data Register */
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#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
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/* Bits 8-31: Reserved */
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#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
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#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
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#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
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/* Bits 8-31: Reserved */
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/* I2C Slave address mask registers:
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*
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* I2C Slave address mask register 0
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* I2C Slave address mask register 1
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* I2C Slave address mask register 2
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* I2C Slave address mask register 3
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*/
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/* Bit 0: Reserved */
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#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
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#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
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/* Bits 8-31: Reserved */
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/* SCH Duty Cycle Register High Half Word */
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#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
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/* Bits 16-31: Reserved */
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/* SCL Duty Cycle Register Low Half Word */
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#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
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/* Bits 16-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_I2C_H */
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