119 lines
5.5 KiB
C
119 lines
5.5 KiB
C
/************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-reset.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */
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#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */
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#define PIC32MX_RESET_RCONSET_OFFSET 0x0008 /* RCON set register */
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#define PIC32MX_RESET_RCONINV_OFFSET 0x000c /* RCON invert register */
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#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */
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#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */
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#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */
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#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */
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/* Register Addresses ***************************************************************/
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#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET)
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#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET)
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#define PIC32MX_RESET_RCONSET (PIC32MX_RESET_K1BASE+PIC32MX_RCONSET_OFFSET)
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#define PIC32MX_RESET_RCONINV (PIC32MX_RESET_K1BASE+PIC32MX_RCONINV_OFFSET)
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#define PIC32MX_RESET_RSWRST (PIC32MX_RESET_K1BASE+PIC32MX_RSWRST_OFFSET)
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#define PIC32MX_RESET_RSWRSTCLR (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTCLR_OFFSET)
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#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET)
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#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Reset control register */
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#define RESET_RCON_POR (1 << 0) /* Bit 0: Power on reset */
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#define RESET_RCON_BOR (1 << 1) /* Bit 1: Brown out reset */
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#define RESET_RCON_IDLE (1 << 2) /* Bit 2: Wake from idle */
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#define RESET_RCON_SLEEP (1 << 3) /* Bit 3: Wake from sleep */
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#define RESET_RCON_WDTO (1 << 4) /* Bit 4: Watchdog timer time-out */
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#define RESET_RCON_SWR (1 << 6) /* Bit 6: Software reset */
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#define RESET_RCON_EXTR (1 << 7) /* Bit 7: External reset pin */
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#define RESET_RCON_VREGS (1 << 8) /* Bit 8: Voltage regulator standby enable */
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#define RESET_RCON_CMR (1 << 9) /* Bit 9: Configuration mismatch reset */
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/* Software reset register */
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#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H */
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