195 lines
9.9 KiB
C
195 lines
9.9 KiB
C
/****************************************************************************
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* arch/hc/src/m9s12/m9s12_flash.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_HC_SRC_M9S12_M9S12_FLASH_H
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#define __ARCH_HC_SRC_M9S12_M9S12_FLASH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Flash memory map *********************************************************
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*
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* 0x4000-0x7fff: 16Kb Fixed FLASH EEPROM (Page 3e)
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* 0x8000-0xbfff: 16Kb Page window
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* 0xc000-0xffff: 16Kb Fixed FLASH EEPROM (Page 3f)
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* (see chip.h)
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*
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* The M9S12 implements 6 bits of the PPAGE register which gives it a
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* 1 Mbyte program memory address space that is accessed through the PPAGE
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* window. The lower 768K portion of the address space, accessed with PPAGE
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* values $00 through $2F, is reserved for external memory when the part is
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* operated in expanded mode. The upper 256K of the address space, accessed
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* with PPAGE values $30 through $3F.
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*/
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#define HCS12_BTLDR_BASE 0xf800 /* 0xf800-0xffff: 2Kb Protected bootloader FLASH */
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/* User-Accessible utility subroutines provided by the serial monitor:
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*
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* PutChar - Sends the character in A out SCI0
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*
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* PutChar: brclr SCI0SR1,TDRE,PutChar ;wait for Tx ready
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* staa SCI0DRL ;send character from A
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* rts
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*
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* GetChar - Wait indefinitely for a character to be received via SCI.
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* Return received character in A.
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*
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* GetChar: brset SCI0SR1,RDRF,RxReady ;exit loop when RDRF=1
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* bra GetChar ;loop till RDRF set
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* RxReady: ldaa SCI0DRL ;read character into A
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* rts ;return
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* EraseAllCmd - Use repeated page erase commands to erase all flash
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* except bootloader in protected block at the end of flash,
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* and mass erase all EEPROM locations
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* DoOnStack - Copy to stack and execute from RAM
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* WriteD2IX - Write the data in D (word) to the address in IX
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* The location may be RAM, FLASH, EEPROM, or a register
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* if FLASH or EEPROM, the operation is completed before return
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* IX and A preserved, returns Z=1 (.EQ.) if OK
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*/
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#ifdef CONFIG_HCS12_SERIALMON
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# define PutChar 0xfee6 /* Sends the character in A out SCI0 */
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# define GetChar 0xfee9 /* Return character received from SCIO in A */
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# define EraseAllCmd 0xfeec /* Erase all flash (except bootloader) */
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# define DoOnStack 0xfeef /* Copy to stack and execute from RAM */
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# define WriteD2IX 0xfef2 /* Write the data in D (word) to the address in IX.
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* The location may be RAM, FLASH, EEPROM, or a register */
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/* Serial monitor version */
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# define SWID_DEVID 0xfef8
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# define SWID_DATE 0xfefa
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# define SWID_YEAR 0xfefc
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# define SWID_VER 0xfefe
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/* Interrupts */
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# define HCS12_UVECTOR_BASE 0xf780 /* 0xf780-0xf7fe: User vector base */
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#endif
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/* FLASH interface */
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#define HCS12_BACKDOOR_KEY 0xff00 /* 0xff00-0xff07: Backdoor comparison keys */
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/* 0xff08-0xff0c: Reserved */
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#define HCS12_FLASH_PROT 0xff0d /* 0xff0d: Flash protection byte */
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/* 0xff0e: Reserved */
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#define HCS12_FLASH_OPT 0xff0f /* 0xff0f: Flash options/security byte */
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/* Interrupts */
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#define HCS12_VECTOR_BASE 0xff80 /* 0xff80-0xfffe: Actual vector base */
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/* Register Offsets *********************************************************/
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#define HCS12_FLASH_FCLKDIV_OFFSET (HCS12_FLASH_BASE+0x00) /* Flash Clock Divider Register */
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#define HCS12_FLASH_FSEC_OFFSET (HCS12_FLASH_BASE+0x03) /* Flash Security Register */
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#define HCS12_FLASH_FCNFG_OFFSET (HCS12_FLASH_BASE+0x03) /* Flash Configuration Register */
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#define HCS12_FLASH_FPROT_OFFSET (HCS12_FLASH_BASE+0x04) /* Flash Protection Register */
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#define HCS12_FLASH_FSTAT_OFFSET (HCS12_FLASH_BASE+0x05) /* Flash Status Register */
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#define HCS12_FLASH_FCMD_OFFSET (HCS12_FLASH_BASE+0x06) /* Flash Command Register */
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#define HCS12_FLASH_FADDRHI_OFFSET (HCS12_FLASH_BASE+0x08) /* Flash High Address Register */
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#define HCS12_FLASH_FADDRLO_OFFSET (HCS12_FLASH_BASE+0x09) /* Flash Low Address Register */
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#define HCS12_FLASH_FDATAHI_OFFSET (HCS12_FLASH_BASE+0x0a) /* Flash High Data Register */
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#define HCS12_FLASH_FDATALO_OFFSET (HCS12_FLASH_BASE+0x0b) /* Flash Low Data Register (*/
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/* Register Addresses *******************************************************/
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#define HCS12_FLASH_FCLKDIV (HCS12_REG_BASE+HCS12_FLASH_FCLKDIV_OFFSET)
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#define HCS12_FLASH_FSEC (HCS12_REG_BASE+HCS12_FLASH_FSEC_OFFSET)
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#define HCS12_FLASH_FCNFG (HCS12_REG_BASE+HCS12_FLASH_FCNFG_OFFSET)
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#define HCS12_FLASH_FPROT (HCS12_REG_BASE+HCS12_FLASH_FPROT_OFFSET)
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#define HCS12_FLASH_FSTAT (HCS12_REG_BASE+HCS12_FLASH_FSTAT_OFFSET)
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#define HCS12_FLASH_FCMD (HCS12_REG_BASE+HCS12_FLASH_FCMD_OFFSET)
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#define HCS12_FLASH_FADDRHI (HCS12_REG_BASE+HCS12_FLASH_FADDRHI_OFFSET)
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#define HCS12_FLASH_FADDRLO (HCS12_REG_BASE+HCS12_FLASH_FADDRLO_OFFSET)
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#define HCS12_FLASH_FDATAHI (HCS12_REG_BASE+HCS12_FLASH_FDATAHI_OFFSET)
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#define HCS12_FLASH_FDATALO (HCS12_REG_BASE+HCS12_FLASH_FDATALO_OFFSET)
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/* Register Bit Definitions *************************************************/
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#define FLASH_FCLKDIV_FDIV_SHIFT (0) /* Bits 0-5: Clock Divider Bits */
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#define FLASH_FCLKDIV_FDIV_MASK (0x3f << FLASH_FCLKDIV_FDIV_SHIFT)
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#define FLASH_FCLKDIV_PRDIV8 (1 << 6) /* Bit 6: Enable Prescaler by 8 */
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#define FLASH_FCLKDIV_FDIVLD (1 << 7) /* Bit 7: Clock Divider Loaded */
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#define FLASH_FSET_SEC_SHIFT (0) /* Bits 0-1: Memory Security Bits */
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#define FLASH_FSET_SEC_MASK (3 << FLASH_FSET_SEC_SHIFT)
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# define FLASH_FSET_SEC_UNSECURED (2 << FLASH_FSET_SEC_SHIFT)
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#define FLASH_FSET_KEYEN (1 << 7) /* Bit 7: Backdoor Key Enable */
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#define FLASH_FSET_NV_SHIFT (2) /* Bits 2-6: Nonvolatile Flag Bits */
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#define FLASH_FSET_NV_MASK (0x1f << FLASH_FSET_NV_SHIFT)
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#define FLASH_FCNG_KEYACC (1 << 5) /* Bit 5: Enable Security Key Writing */
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#define FLASH_FCNG_CCIE (1 << 6) /* Bit 6: Command Complete Interrupt Enable */
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#define FLASH_FCNG_CBEIE (1 << 7) /* Bit 7: Command Buffer Empty Interrupt Enable */
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#define FLASH_FPROT_FPLS_SHIFT (0) /* Bits 0-1: Flash Protection Lower Address Size */
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#define FLASH_FPROT_FPLS_MASK (3 << FLASH_FPROT_FPLS_SHIFT)
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# define FLASH_FPROT_FPLS_512B (0 << FLASH_FPROT_FPLS_SHIFT)
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# define FLASH_FPROT_FPLS_1KB (1 << FLASH_FPROT_FPLS_SHIFT)
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# define FLASH_FPROT_FPLS_2KB (2 << FLASH_FPROT_FPLS_SHIFT)
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# define FLASH_FPROT_FPLS_4KB (3 << FLASH_FPROT_FPLS_SHIFT)
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#define FLASH_FPROT_FPLDIS (1 << 2) /* Bit 2: Flash Protection Lower address range Disable */
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#define FLASH_FPROT_FPHS_SHIFT (3) /* Bits 3-4: Flash Protection Higher Address Size */
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#define FLASH_FPROT_FPHS_MASK (3 << FLASH_FPROT_FPHS_SHIFT)
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# define FLASH_FPROT_FPHS_2KB (0 << FLASH_FPROT_FPHS_SHIFT)
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# define FLASH_FPROT_FPHS_4KB (1 << FLASH_FPROT_FPHS_SHIFT)
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# define FLASH_FPROT_FPHS_8KB (2 << FLASH_FPROT_FPHS_SHIFT)
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# define FLASH_FPROT_FPHS_16KB (3 << FLASH_FPROT_FPHS_SHIFT)
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#define FLASH_FPROT_FPHDIS (1 << 5) /* Bit 5: Flash Protection Higher address range disable */
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#define FLASH_FPROT_FPOPEN (1 << 7) /* Bit 7: Opens the Flash block for program or erase */
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#define FLASH_FSTAT_BLANK (1 << 2) /* Bit 2: Array has been verified as erased */
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#define FLASH_FSTAT_ACCERR (1 << 4) /* Bit 4: Flash access error */
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#define FLASH_FSTAT_PVIOL (1 << 5) /* Bit 5: Protection violation */
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#define FLASH_FSTAT_CCIF (1 << 6) /* Bit 6: Command complete interrupt flag */
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#define FLASH_FSTAT_CBEIF (1 << 7) /* Bit 7: Command buffer empty interrupt flag */
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#define FLASH_FCMD_ERASEVERIFY 0x05 /* Erase Verify */
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#define FLASH_FCMD_WORDPROGRM 0x20 /* Word Program */
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#define FLASH_FCMD_SECTORERASE 0x40 /* Sector Erase */
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#define FLASH_FCMD_MASSERASE 0x41 /* Mass Erase */
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#define FLASH_FADDRHI_MASK 0x7f
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_HC_SRC_M9S12_M9S12_FLASH_H */
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