493b8de938
This reverts commit f735584514.
These header changes introduce unacceptable errors:
1. The changes alter the width of the initial block comment. That will cause nxstyle failures on most of the files.
2. The third line of the header is an (optional) short description of content of the the file. This change erroneously removes that line.
Automated header file changes can screw up a lot of files, very quickly.
220 lines
14 KiB
C
220 lines
14 KiB
C
/****************************************************************************************************
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* arch/arm/include/sama5/chip.h
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*
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* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_SAMA5_CHIP_H
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#define __ARCH_ARM_INCLUDE_SAMA5_CHIP_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* SAMA5D2 Family
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*
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* SAMA5D21 SAMA5D22 SAMA5D23 SAMA5D24 SAMA5D26 SAMA5D27 SAMA5D28
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* ------------------------- --------- --------- --------- --------- --------- --------- ---------
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* Pin Count 196 196 196 256 289 289 289
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* Max. Operating Frequency 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz
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* CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5
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* Max I/O Pins 72 72 72 105 128 128 128
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* USB Transceiver 1 1 1 1 1 1 1
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* USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed
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* USB Interface 2 2 2 3 3 3 3
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* SPI 6 6 6 7 7 7 7
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* QuadSPI 2 2 2 2 2 2 2
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* TWIHS (I2C) 6 6 6 7 7 7 7
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* UART 9 9 9 10 10 10 10
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* CAN - 1 1 - - 2 2
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* SDIO/SD/MMC 1 1 1 2 2 2 2
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* I2SC 2 2 2 2 2 2 2
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* SSC 2 2 2 2 2 2 2
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* Class D 1 1 1 2 2 2 2
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* PDMIC 1 1 1 2 2 2 2
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* Camera Interface 1 1 1 1 1 1 1
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* ADC Inputs 5 5 5 12 12 12 12
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* AESB - 1 1 1 - 1 1
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* SRAM (Kbytes) 128 128 128 128 128 128 128
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* DDR Bus 16-bit 16-bit 16-bit 16/32-bit 16/32-bit 16/32-bit 16/32-bit
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* Timers 6 6 6 6 6 6 6
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* Tamper pins 6 6 6 2 8 8 8
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* Packages BGA196 BGA196 BGA196 BGA256 BGA289 BGA289 BGA289
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*/
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#if defined(CONFIG_ARCH_CHIP_ATSAMA5D21) || defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || \
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defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || defined(CONFIG_ARCH_CHIP_ATSAMA5D23) || \
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defined(CONFIG_ARCH_CHIP_ATSAMA5D24) || defined(CONFIG_ARCH_CHIP_ATSAMA5D26) || \
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defined(CONFIG_ARCH_CHIP_ATSAMA5D27) || defined(CONFIG_ARCH_CHIP_ATSAMA5D28)
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# define ATSAMA5D2 1 /* SAMA5D2 family */
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# undef ATSAMA5D3 /* Not SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (128*1024) /* SRAM0: 128KB */
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#ifdef CONFIG_ARMV7A_L2CC_PL310
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# define SAM_ISRAM1_SIZE (0) /* (SRAM1 used for L2 cache )*/
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#else
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# define SAM_ISRAM0_SIZE (64*1024) /* SRAM1: 128KB */
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#endif
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# define SAM_NDMAC 2 /* (2) XDMA controllers */
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# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
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/* SAMA5D3 Family
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*
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* ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 ATSAMA5D36
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* ------------------------- ------------- ------------- ------------- ------------- -------------
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* Pin Count 324 324 324 324 324
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* Max. Operating Frequency 536 MHz 536 MHz 536 MHz 536 MHz 536 MHz
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* CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5
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* Max I/O Pins 160 160 160 160 160
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* Ext Interrupts 160 160 160 160 160
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* USB Transceiver 3 3 3 3 3
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* USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed
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* USB Interface Host, Device Host, Device Host, Device Host, Device Host, Device
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* SPI 6 6 6 6 6
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* TWI (I2C) 3 3 3 3 3
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* UART 7 5 5 7 7
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* CAN - - 2 2 2
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* LIN 4 4 4 4 4
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* SSC 2 2 2 2 2
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* Ethernet 1 1 1 2 2
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* SD / eMMC 3 2 3 2 3
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* Graphic LCD Yes Yes Yes - Yes
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* Camera Interface Yes Yes Yes Yes Yes
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* ADC channels 12 12 12 12 12
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* ADC Resolution (bits) 12 12 12 12 12
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* ADC Speed (ksps) 440 440 440 440 1000
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* Resistive Touch Screen Yes Yes Yes Yes Yes
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* Crypto Engine AES/DES/ AES/DES/ AES/DES/ AES/DES/ AES/DES/
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* SHA/TRNG SHA/TRNG SHA/TRNG SHA/TRNG SHA/TRNG
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* SRAM (Kbytes) 128 128 128 128 128
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* External Bus Interface 1 1 1 1 1
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* DRAM Memory DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR,
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* SDRAM/LPSDR SDRAM/LPSDR DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR,
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* NAND Interface Yes Yes Yes Yes Yes
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* Temp. Range (deg C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 105
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* I/O Supply Class 1.8/3.3 1.8/3.3 1.8/3.3 1.8/3.3 1.8/3.3
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* Operating Voltage (Vcc) 1.08 to 1.32 1.08 to 1.32 1.08 to 1.32 1.08 to 1.322 1.08 to 1.32
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* FPU Yes Yes Yes Yes Yes
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* MPU / MMU No/Yes No/Yes No/Yes No/Yes No/Yes
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* Timers 5 5 5 6 6
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* Output Compare channels 6 6 6 6 6
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* Input Capture Channels 6 6 6 6 6
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* PWM Channels 4 4 4 4 4
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* 32kHz RTC Yes Yes Yes Yes Yes
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* Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A
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*/
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# define ATSAMA5D3 1 /* SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) DMA controllers */
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# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# define ATSAMA5D3 1 /* SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) DMA controllers */
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# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# define ATSAMA5D3 1 /* SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) DMA controllers */
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# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# define ATSAMA5D3 1 /* SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) DMA controllers */
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# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D36)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# define ATSAMA5D3 1 /* SAMA5D3 family */
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# undef ATSAMA5D4 /* Not SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) DMA controllers */
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# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
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/* The SAMA5D4 series devices are similar to the SAMA5D3 family except that:
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*
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* - Some parts support a 32-bit DDR data path (SAMA5D42 and SAMA5D44)
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* - Some parts support a Video Decoder (SAMA5D43 and SAMA5D44)
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* - Includes an L2 data cache, NEON FPU, and TrustZone
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* - New XDMAC DMA controller
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* - There are few differences in the support peripherals. As examples:
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* Gigbit Ethernet is not supported, for example; 10/100Base-T Ethernet
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* is different. Additional instances of peripherals: USART4, TWI3,
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* and SPI2.
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*/
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \
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defined(CONFIG_ARCH_CHIP_ATSAMA5D43) || defined(CONFIG_ARCH_CHIP_ATSAMA5D44)
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# undef ATSAMA5D2 /* Not SAMA5D2 family */
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# undef ATSAMA5D3 /* Not SAMA5D3 family */
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# define ATSAMA5D4 1 /* SAMA5D4 family */
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# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
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# define SAM_ISRAM1_SIZE (64*1024)
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# define SAM_NDMAC 2 /* (2) XDMA controllers */
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# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
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#else
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# error Unrecognized SAMAD5 chip
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#endif
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_SAMA5_CHIP_H */
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