145 lines
4.9 KiB
C
145 lines
4.9 KiB
C
/****************************************************************************
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* configs/misoc/include/generated/common.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Ramtin Amin <keytwo@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H
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#define __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H
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/****************************************************************************
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* Included Filese
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****************************************************************************/
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#include "hw/common.h"
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#include "hw/flags.h"
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#include <arch/board/generated/csr.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define DFII_NPHASES 1
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
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#define command_prd(X) command_p0(X)
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#define command_pwr(X) command_p0(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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/****************************************************************************
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* Private Data
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****************************************************************************/
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const unsigned int sdram_dfii_pix_wrdata_addr[1] =
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{
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR
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};
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const unsigned int sdram_dfii_pix_rddata_addr[1] =
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{
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static void cdelay(int i);
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static void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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static void init_sequence(void)
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{
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE | DFII_CONTROL_ODT |
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DFII_CONTROL_RESET_N);
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cdelay(20000);
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/* Precharge All */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS);
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/* Load Mode Register / Reset DLL, CL=2, BL=1 */
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sdram_dfii_pi0_address_write(0x120);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE |
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DFII_COMMAND_CS);
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cdelay(200);
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/* Precharge All */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS);
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/* Auto Refresh */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS);
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cdelay(4);
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/* Auto Refresh */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS);
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cdelay(4);
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/* Load Mode Register / CL=2, BL=1 */
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sdram_dfii_pi0_address_write(0x20);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE |
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DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H
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