205 lines
8.0 KiB
C
205 lines
8.0 KiB
C
/****************************************************************************
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* boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The B-U585I-IOT02A board supports both HSE and LSE crystals (X1 and X2).
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* However, as shipped, the X1 crystal is not populated. Therefore the board
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* will need to run off the 32kHz-sync'ed MSIS.
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*
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* System Clock source : PLL (MSIS)
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* SYSCLK(Hz) : 160000000 Determined by PLL configuration
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* HCLK(Hz) : 160000000
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* AHB Prescaler : 1 (STM32_RCC_CFGR2_HPRE) (160MHz)
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* APB1 Prescaler : 1 (STM32_RCC_CFGR2_PPRE1) (160MHz)
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* APB2 Prescaler : 1 (STM32_RCC_CFGR2_PPRE2) (160MHz)
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* APB3 Prescaler : 1 (STM32_RCC_CFGR3_PPRE3) (160MHz)
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* MSIS Frequency(Hz) : 4000000 (nominal)
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* MSIK Frequency(Hz) : 4000000 (nominal)
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* PLL_MBOOST : 1 (Embedded power distribution booster)
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* PLLM : 1 (STM32_PLLCFG_PLLM)
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* PLLN : 80 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 2 (STM32_PLLCFG_PLLQ)
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* PLLR : 2 (STM32_PLLCFG_PLLR)
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* Flash Latency(WS) : 4
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - 4 MHz, autotrimmed via LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_LSE_FREQUENCY 32768
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#define STM32_BOARD_USEMSIS 1
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#define STM32_BOARD_MSISRANGE RCC_ICSCR1_MSISRANGE_4MHZ
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#define STM32_BOARD_MSIKRANGE RCC_ICSCR1_MSIKRANGE_4MHZ
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/* PLL1 config; we use this to generate our system clock */
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#define STM32_RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(1)
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#define STM32_RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(80)
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#define STM32_RCC_PLL1DIVR_PLL1P 0
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#undef STM32_RCC_PLL1CFGR_PLL1P_ENABLED
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#define STM32_RCC_PLL1DIVR_PLL1Q 0
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#undef STM32_RCC_PLL1CFGR_PLL1Q_ENABLED
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#define STM32_RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R(2)
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#define STM32_RCC_PLL1CFGR_PLL1R_ENABLED
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#define STM32_SYSCLK_FREQUENCY 160000000ul
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/* Enable LSE (for the RTC and for MSIS autotrimming) */
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#define STM32_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* Configure the APB1 prescaler */
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#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Configure the APB3 prescaler */
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#define STM32_RCC_CFGR3_PPRE3 RCC_CFGR3_PPRE3_HCLK /* PCLK3 = HCLK / 1 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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/* The timer clock frequencies are automatically defined by hardware. If the
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* APB prescaler equals 1, the timer clock frequencies are set to the same
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* frequency as that of the APB domain. Otherwise they are set to twice.
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* Note: TIM1,15,16 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY
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/* DMA Channel/Stream Selections ********************************************/
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/* Alternate function pin selections ****************************************/
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/* USART1: Connected to STLink VCP and to CN10 with small rework of pcb. */
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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/* SPI1: Arduino Connector CN13 */
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#define GPIO_SPI1_NSS (GPIO_OUTPUT|GPIO_SPEED_2MHZ| \
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GPIO_PUSHPULL|GPIO_OUTPUT_SET| \
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GPIO_PORTE|GPIO_PIN12) /* PE12 */
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#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_4|GPIO_SPEED_25MHZ) /* PE13 */
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#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_4) /* PE14 */
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#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_4|GPIO_SPEED_25MHZ) /* PE15 */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_4 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_board_initialize
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*
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* Description:
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* All STM32 architectures must provide the following entry point.
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* This entry point is called early in the initialization -- after all
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* memory has been configured and mapped but before any devices
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* have been initialized.
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*
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****************************************************************************/
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void stm32_board_initialize(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */
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