94 lines
4.1 KiB
C
94 lines
4.1 KiB
C
/****************************************************************************
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* arch/arm/src/lpc214x/lpc214x_pll.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
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#define __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* PLL bass addresses *******************************************************/
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/* There are two PLLs:
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* PLL0 generates CCLK and
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* PLL1 is configured to provide the 48MHx USB clock
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*/
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#define LPC214X_PLL0_BASE (LPC214X_PLL_BASE)
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#define LPC214X_PLL1_BASE (LPC214X_PLL_BASE + 0x00000020)
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/* PLL registers ************************************************************/
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#define LPC214x_PLL0_CON (LPC214X_PLL0_BASE+LPC214X_PLL_CON_OFFSET)
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#define LPC214x_PLL0_CFG (LPC214X_PLL0_BASE+LPC214X_PLL_CFG_OFFSET)
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#define LPC214x_PLL0_STAT (LPC214X_PLL0_BASE+LPC214X_PLL_STAT_OFFSET)
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#define LPC214x_PLL0_FEED (LPC214X_PLL0_BASE+LPC214X_PLL_FEED_OFFSET)
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#define LPC214x_PLL1_CON (LPC214X_PLL1_BASE+LPC214X_PLL_CON_OFFSET)
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#define LPC214x_PLL1_CFG (LPC214X_PLL1_BASE+LPC214X_PLL_CFG_OFFSET)
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#define LPC214x_PLL1_STAT (LPC214X_PLL1_BASE+LPC214X_PLL_STAT_OFFSET)
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#define LPC214x_PLL1_FEED (LPC214X_PLL1_BASE+LPC214X_PLL_FEED_OFFSET)
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/* Register bit settings ****************************************************/
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/* PLL Control Register Bit Settings */
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#define LPC214X_PLL_CON_PLLE (1 << 0) /* PLL Enable */
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#define LPC214X_PLL_CON_PLLC (1 << 1) /* PLL Connect */
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/* PLL Configuration Register Bit Settings */
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#define LPC214X_PLL_CFG_MSEL (0x1f << 0) /* PLL Multiplier (minus 1) */
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#define LPC214X_PLL_CFG_PSEL (0x03 << 5) /* PLL Divider (encoded) */
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#define LPC214X_PLL_CFG_PSEL1 (0x00 << 5)
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#define LPC214X_PLL_CFG_PSEL2 (0x01 << 5)
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#define LPC214X_PLL_CFG_PSEL4 (0x02 << 5)
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#define LPC214X_PLL_CFG_PSEL8 (0x03 << 5)
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/* PLL Status Register Bit Settings */
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#define LPC214X_PLL_STAT_MSEL (0x1f << 0) /* PLL Multiplier Readback */
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#define LPC214X_PLL_STAT_PSEL (0x03 << 5) /* PLL Divider Readback */
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#define LPC214X_PLL_STAT_PLLE (1 << 8) /* PLL Enable Readback */
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#define LPC214X_PLL_STAT_PLLC (1 << 9) /* PLL Connect Readback */
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#define LPC214X_PLL_STAT_PLOCK (1 << 10) /* PLL Lock Status */
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/* PLL Feed Register values */
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#define LPC214X_PLL_FEED1 0xaa
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#define LPC214X_PLL_FEED2 0x55
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H */
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