908df725ad
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
157 lines
4.7 KiB
C
157 lines
4.7 KiB
C
/****************************************************************************
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* arch/mips/include/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_MIPS_INCLUDE_IRQ_H
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#define __ARCH_MIPS_INCLUDE_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <sys/types.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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#endif
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/* Include NuttX-specific IRQ definitions */
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#include <nuttx/irq.h>
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/* Include chip-specific IRQ definitions (including IRQ numbers) */
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#include <arch/chip/irq.h>
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/* Include AVR architecture-specific IRQ definitions (including register
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* save structure and up_irq_save()/up_irq_restore() macros
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*/
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#ifdef CONFIG_ARCH_MIPS32
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# include <arch/mips32/irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/* Return the current value of the stack pointer */
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static inline uint32_t up_getsp(void)
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{
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register uint32_t sp;
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__asm__
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(
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"\tadd %0, $0, $29\n"
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: "=r"(sp)
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);
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return sp;
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}
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_current_regs holds a references to the current interrupt level
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* register storage structure. It is non-NULL only during interrupt
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* processing. Access to g_current_regs must be through the
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* [get/set]_current_regs for portability.
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*/
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/* For the case of architectures with multiple CPUs, then there must be one
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* such value for each processor that can receive an interrupt.
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*/
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EXTERN volatile uint32_t *g_current_regs;
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: up_cpu_index
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*
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* Description:
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* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
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* corresponds to the currently executing CPU.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
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* corresponds to the currently executing CPU.
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*
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****************************************************************************/
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#define up_cpu_index() (0)
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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static inline_function uint32_t *up_current_regs(void)
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{
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return (uint32_t *)g_current_regs;
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}
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static inline_function void up_set_current_regs(uint32_t *regs)
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{
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g_current_regs = regs;
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}
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/****************************************************************************
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* Name: up_interrupt_context
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*
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* Description:
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* Return true is we are currently executing in the interrupt
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* handler context.
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*
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****************************************************************************/
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#define up_interrupt_context() (up_current_regs() != NULL)
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_INCLUDE_IRQ_H */
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