471 lines
16 KiB
C
471 lines
16 KiB
C
/****************************************************************************
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* boards/arm/stm32f7/stm32f769i-disco/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Do not include STM32F7 header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The STM32F7 Discovery board provides the following clock sources:
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*
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* X2: 25 MHz oscillator for STM32F769NIH6 microcontroller
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* and Ethernet PHY.
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* X1: 32.768 KHz crystal for STM32F769NIH6 embedded RTC
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: On-board crystal frequency is 25MHz
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 25000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 25,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
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* and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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#if defined(CONFIG_STM32F7_OTGFS)
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/* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz
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* SYSCLK = 384 MHz / 2 = 192 MHz
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* USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz
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* DSI CLK = PLL_VCO / PLLR = 384 / 7 = 54,86 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(7)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 384)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8)
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#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG)
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/* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
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* DSI CLK = PLL_VCO / PLLR = 432 / 8 = 54 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(8)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#else
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/* No restrictions by OTGFS
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
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* DSI CLK = PLL_VCO / PLLR = 432 / 8 = 54 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(8)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#endif
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/* Configure factors for PLLSAI clock */
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
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#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions **********************************************************/
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/* The STM32F769I-DISCO board has numerous LEDs but only one, LD1 located
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* near the reset button, that can be controlled by software
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* (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is controlled
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* by the ST-Link).
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*
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* LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino
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* interface. One end of LD1 is grounded so a high output on PI1 will
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* illuminate the LED.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_NLEDS 1
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#define BOARD_LD1 BOARD_LED1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c.
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* The LEDs are used to encode OS-related events as follows:
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*
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* SYMBOL Meaning LD1
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* ------------------- ----------------------- ------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt N/C
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* LED_SIGNAL In a signal handler N/C
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* LED_ASSERTION An assertion failed N/C
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* LED_PANIC The system has crashed FLASH
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*
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* Thus is LD1 is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If LD1 is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*/
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#define LED_STARTED 0 /* LD1=OFF */
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#define LED_HEAPALLOCATE 0 /* LD1=OFF */
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#define LED_IRQSENABLED 0 /* LD1=OFF */
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#define LED_STACKCREATED 1 /* LD1=ON */
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#define LED_INIRQ 2 /* LD1=no change */
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#define LED_SIGNAL 2 /* LD1=no change */
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#define LED_ASSERTION 2 /* LD1=no change */
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#define LED_PANIC 3 /* LD1=flashing */
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/* Button definitions *******************************************************/
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/* The STM32F7 Discovery supports one button:
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* Pushbutton B1, labelled "User", is connected to GPIO PA0.
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* A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* USART6:
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*
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* These configurations assume that you are using a standard Arduio RS-232
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* shield with the serial interface with RX on pin D0 and TX on pin D1:
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*
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* -------- ---------------
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* STM32F7
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* ARDUINO FUNCTION GPIO
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* -- ----- --------- -----
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* DO RX USART6_RX PC7
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* D1 TX USART6_TX PC6
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* -- ----- --------- -----
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*/
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#define GPIO_USART6_RX GPIO_USART6_RX_1
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#define GPIO_USART6_TX GPIO_USART6_TX_1
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/* USART1:
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* USART1 is connected to the "Virtual Com Port" lines
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* of the ST-LINK controller.
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*
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* -------- ---------------
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* STM32F7
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* SIGNAME FUNCTION GPIO
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* -- ----- --------- -----
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* VCP_RX USART1_RX PA10
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* VCP_TX USART1_TX PA9
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* -- ----- --------- -----
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*/
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#define GPIO_USART1_RX GPIO_USART1_RX_1
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#define GPIO_USART1_TX GPIO_USART1_TX_1
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/* PWM
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*
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* The STM32F7 Discovery has no real on-board PWM devices, but the board can
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* be configured to output a pulse train using TIM1 CH4 on PA11.
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*/
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#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1
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/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
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*
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* STM32 F7 BOARD LAN8742A
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PG11 RMII_TX_EN TXEN
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* PG13 RMII_TXD0 TXD0
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* PG14 RMII_TXD1 TXD1
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* PC4 RMII_RXD0 RXD0/MODE0
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* PC5 RMII_RXD1 RXD1/MODE1
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* PD5 RMII_RXER RXER/PHYAD0
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* PA7 RMII_CRS_DV CRS_DV/MODE2
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* PC1 RMII_MDC MDC
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* PA2 RMII_MDIO MDIO
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* N/A NRST nRST
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* PA1 RMII_REF_CLK nINT/REFCLK0
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* N/A OSC_25M XTAL1/CLKIN
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*
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* The PHY address is 0, since RMII_RXER/PHYAD0 features a pull down.
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* After reset, RMII_RXER/PHYAD0 switches to the RXER function,
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* receive errors can be detected using GPIO pin PD5
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*/
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
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/* I2C Mapping
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* I2C #4 is connected to the LCD daughter board
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* and the WM8994 audio codec.
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*
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* I2C4_SCL - PD12
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* I2C4_SDA - PB7
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*/
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#define GPIO_I2C4_SCL GPIO_I2C4_SCL_1
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#define GPIO_I2C4_SDA GPIO_I2C4_SDA_5
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/* SDMMC */
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/* Stream selections are arbitrary for now but might become important in the
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* future if we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDMMC1_1 = Channel 4, Stream 3
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* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
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*
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* DMAMAP_SDMMC2_1 = Channel 11, Stream 0
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* DMAMAP_SDMMC2_2 = Channel 11, Stream 5
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*/
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/* #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 */
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#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* SDMMC2 Pin mapping
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*
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* D0 - PG9
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* D1 - PG10
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* D2 - PB3
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* D3 - PB4
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*/
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#define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_2
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#define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_2
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#define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
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#define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
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/* LCD DISPLAY
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* (work in progress as of 2017 07 19)
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*/
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#define BOARD_LTDC_WIDTH 800
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#define BOARD_LTDC_HEIGHT 472
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#define BOARD_LTDC_HSYNC 10
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#define BOARD_LTDC_HFP 10
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#define BOARD_LTDC_HBP 20
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#define BOARD_LTDC_VSYNC 2
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#define BOARD_LTDC_VFP 4
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#define BOARD_LTDC_VBP 2
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#define BOARD_LTDC_GCR_PCPOL 0
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#define BOARD_LTDC_GCR_DEPOL 0
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#define BOARD_LTDC_GCR_VSPOL 0
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#define BOARD_LTDC_GCR_HSPOL 0
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#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H */
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