zhengshaobo1 09a81017b8 To solve the problem of unordered setting of div & mux, after solving the problem, the frequency will be set to mux first, and then div ... Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>		2023-09-10 13:36:16 +03:00
..
clk_divider.c	Solve the risk of dividing by 0 when setting frequency points	2023-09-10 13:36:16 +03:00
clk_fixed_factor.c
clk_fixed_rate.c
clk_fractional_divider.c
clk_gate.c
clk_multiplier.c
clk_mux.c	drivers/clk: Change CLK_SET_RATE_NO_REPARENT to CLK_MUX_SET_RATE_NO_REPARENT	2023-09-05 18:05:50 +03:00
clk_phase.c
clk_rpmsg.c
clk.c	To solve the problem of unordered setting of div & mux, after solving the problem, the frequency will be set to mux first, and then div	2023-09-10 13:36:16 +03:00
clk.h
CMakeLists.txt
Kconfig
Make.defs