1f3e7e49b5
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1105 42af7a65-404d-4744-a932-0658087f49c3
138 lines
7.4 KiB
C
138 lines
7.4 KiB
C
/************************************************************************************
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* arch/arm/src/str71x/str71x_pcu.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STR71X_STR71X_PCU_H
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#define __ARCH_ARM_SRC_STR71X_STR71X_PCU_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "str71x_map.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Power Control Unit (PCU) register offsets ****************************************/
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#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */
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#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */
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#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */
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#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */
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#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */
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#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */
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/* Power Control Unit (PCU) register addresses **************************************/
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#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET)
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#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET)
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#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET)
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#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET)
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#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET)
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#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET)
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/* Register bit settings ************************************************************/
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/* PCU RSTR register bit definitions */
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#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */
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/* PCU PLL2CR register bit definitions */
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#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */
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#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */
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#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */
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#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */
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#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */
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#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */
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#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */
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#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */
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#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */
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#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */
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#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */
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#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */
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#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */
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#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */
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#define STR71X_PCUPPL2CR_FRRRNG (0x0040) /* Bit 6: PLL2 frequency range selection */
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#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */
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#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */
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#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */
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#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */
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#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */
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/* PCU BOOTCR register bit definitions */
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#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */
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#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */
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#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */
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#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */
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#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */
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#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */
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#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */
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#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */
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#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */
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#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */
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#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */
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/* PCU PWRCR register bit definitions */
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#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */
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#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */
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#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */
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#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */
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#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */
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#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */
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#define STR71X_PCUPWRCR_LVDDIS (0x0200) /* Bit 9: FLASH low speed (low power) select */
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#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */
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#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */
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#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STR71X_STR71X_PCU_H */
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