807 lines
24 KiB
C
807 lines
24 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_wwdg.c
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*
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* Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/timers/watchdog.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip/stm32_dbgmcu.h"
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#include "stm32_wdg.h"
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#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The minimum frequency of the WWDG clock is:
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*
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* Fmin = PCLK1 / 4096 / 8
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*
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* So the maximum delay (in milliseconds) is then:
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*
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* 1000 * (WWDG_CR_T_MAX+1) / Fmin
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*
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* For example, if PCLK1 = 42MHz, then the maximum delay is:
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*
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* Fmin = 1281.74
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* 1000 * 64 / Fmin = 49.93 msec
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*/
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#define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8)
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#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN)
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/* Configuration ************************************************************/
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#ifndef CONFIG_STM32_WWDG_DEFTIMOUT
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# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT
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#endif
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#ifndef CONFIG_DEBUG_WATCHDOG_INFO
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# undef CONFIG_STM32_WWDG_REGDEBUG
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure provides the private representation of the "lower-half"
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* driver state structure. This structure must be cast-compatible with the
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* well-known watchdog_lowerhalf_s structure.
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*/
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struct stm32_lowerhalf_s
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{
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FAR const struct watchdog_ops_s *ops; /* Lower half operations */
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xcpt_t handler; /* Current EWI interrupt handler */
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uint32_t timeout; /* The actual timeout value */
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uint32_t fwwdg; /* WWDG clock frequency */
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bool started; /* The timer has been started */
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uint8_t reload; /* The 7-bit reload field reset value */
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uint8_t window; /* The 7-bit window (W) field value */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Register operations ******************************************************/
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#ifdef CONFIG_STM32_WWDG_REGDEBUG
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static uint16_t stm32_getreg(uint32_t addr);
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static void stm32_putreg(uint16_t val, uint32_t addr);
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#else
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# define stm32_getreg(addr) getreg32(addr)
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# define stm32_putreg(val,addr) putreg32(val,addr)
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#endif
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static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv,
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uint8_t window);
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/* Interrupt hanlding *******************************************************/
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static int stm32_interrupt(int irq, FAR void *context);
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/* "Lower half" driver methods **********************************************/
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static int stm32_start(FAR struct watchdog_lowerhalf_s *lower);
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static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower);
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static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower);
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static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
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FAR struct watchdog_status_s *status);
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static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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uint32_t timeout);
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static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
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xcpt_t handler);
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static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
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unsigned long arg);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* "Lower half" driver methods */
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static const struct watchdog_ops_s g_wdgops =
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{
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.start = stm32_start,
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.stop = stm32_stop,
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.keepalive = stm32_keepalive,
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.getstatus = stm32_getstatus,
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.settimeout = stm32_settimeout,
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.capture = stm32_capture,
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.ioctl = stm32_ioctl,
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};
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/* "Lower half" driver state */
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static struct stm32_lowerhalf_s g_wdgdev;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_getreg
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*
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* Description:
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* Get the contents of an STM32 register
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_WWDG_REGDEBUG
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static uint16_t stm32_getreg(uint32_t addr)
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{
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static uint32_t prevaddr = 0;
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static uint32_t count = 0;
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static uint16_t preval = 0;
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/* Read the value from the register */
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uint16_t val = getreg16(addr);
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/* Is this the same value that we read from the same registe last time? Are
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* we polling the register? If so, suppress some of the output.
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*/
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if (addr == prevaddr && val == preval)
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{
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if (count == 0xffffffff || ++count > 3)
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{
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if (count == 4)
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{
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wdinfo("...\n");
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}
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return val;
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}
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}
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/* No this is a new address or value */
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else
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{
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/* Did we print "..." for the previous value? */
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if (count > 3)
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{
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/* Yes.. then show how many times the value repeated */
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wdinfo("[repeats %d more times]\n", count-3);
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}
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/* Save the new address, value, and count */
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prevaddr = addr;
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preval = val;
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count = 1;
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}
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/* Show the register value read */
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wdinfo("%08x->%04x\n", addr, val);
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return val;
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}
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#endif
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/****************************************************************************
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* Name: stm32_putreg
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*
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* Description:
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* Set the contents of an STM32 register to a value
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_WWDG_REGDEBUG
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static void stm32_putreg(uint16_t val, uint32_t addr)
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{
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/* Show the register value being written */
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wdinfo("%08x<-%04x\n", addr, val);
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/* Write the value */
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putreg16(val, addr);
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}
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#endif
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/****************************************************************************
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* Name: stm32_setwindow
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*
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* Description:
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* Set the CFR window value. The window value is compared to the down-
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* counter when the counter is updated. The WWDG counter should be updated
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* only when the counter is below this window value (and greater than 64)
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* otherwise a reset will be generated
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*
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****************************************************************************/
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static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, uint8_t window)
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{
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uint16_t regval;
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/* Set W[6:0] bits according to selected window value */
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regval = stm32_getreg(STM32_WWDG_CFR);
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regval &= ~WWDG_CFR_W_MASK;
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regval |= window << WWDG_CFR_W_SHIFT;
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stm32_putreg(regval, STM32_WWDG_CFR);
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/* Remember the window setting */
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priv->window = window;
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}
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/****************************************************************************
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* Name: stm32_interrupt
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*
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* Description:
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* WWDG early warning interrupt
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*
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* Input Parameters:
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* Usual interrupt handler arguments.
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*
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* Returned Values:
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* Always returns OK.
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*
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****************************************************************************/
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static int stm32_interrupt(int irq, FAR void *context)
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{
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FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
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uint16_t regval;
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/* Check if the EWI interrupt is really pending */
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regval = stm32_getreg(STM32_WWDG_SR);
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if ((regval & WWDG_SR_EWIF) != 0)
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{
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/* Is there a registered handler? */
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if (priv->handler)
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{
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/* Yes... NOTE: This interrupt service routine (ISR) must reload
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* the WWDG counter to prevent the reset. Otherwise, we will reset
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* upon return.
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*/
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priv->handler(irq, context);
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}
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/* The EWI interrupt is cleared by writing '0' to the EWIF bit in the
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* WWDG_SR register.
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*/
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regval &= ~WWDG_SR_EWIF;
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stm32_putreg(regval, STM32_WWDG_SR);
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}
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return OK;
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}
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/****************************************************************************
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* Name: stm32_start
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*
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* Description:
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* Start the watchdog timer, resetting the time to the current timeout,
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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wdinfo("Entry\n");
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DEBUGASSERT(priv);
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/* The watchdog is always disabled after a reset. It is enabled by setting
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* the WDGA bit in the WWDG_CR register, then it cannot be disabled again
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* except by a reset.
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*/
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stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR);
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priv->started = true;
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return OK;
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}
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/****************************************************************************
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* Name: stm32_stop
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*
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* Description:
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* Stop the watchdog timer
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
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{
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/* The watchdog is always disabled after a reset. It is enabled by setting
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* the WDGA bit in the WWDG_CR register, then it cannot be disabled again
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* except by a reset.
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*/
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wdinfo("Entry\n");
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return -ENOSYS;
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}
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/****************************************************************************
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* Name: stm32_keepalive
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*
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* Description:
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* Reset the watchdog timer to the current timeout value, prevent any
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* imminent watchdog timeouts. This is sometimes referred as "pinging"
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* the watchdog timer or "petting the dog".
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*
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* The application program must write in the WWDG_CR register at regular
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* intervals during normal operation to prevent an MCU reset. This operation
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* must occur only when the counter value is lower than the window register
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* value. The value to be stored in the WWDG_CR register must be between
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* 0xff and 0xC0:
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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wdinfo("Entry\n");
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DEBUGASSERT(priv);
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/* Write to T[6:0] bits to configure the counter value, no need to do
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* a read-modify-write; writing a 0 to WDGA bit does nothing.
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*/
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stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR);
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return OK;
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}
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/****************************************************************************
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* Name: stm32_getstatus
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*
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* Description:
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* Get the current watchdog timer status
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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* status - The location to return the watchdog status information.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
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FAR struct watchdog_status_s *status)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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uint32_t elapsed;
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uint16_t reload;
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wdinfo("Entry\n");
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DEBUGASSERT(priv);
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/* Return the status bit */
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status->flags = WDFLAGS_RESET;
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if (priv->started)
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{
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status->flags |= WDFLAGS_ACTIVE;
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}
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if (priv->handler)
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{
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status->flags |= WDFLAGS_CAPTURE;
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}
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/* Return the actual timeout is milliseconds */
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status->timeout = priv->timeout;
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/* Get the time remaining until the watchdog expires (in milliseconds) */
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reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f;
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elapsed = priv->reload - reload;
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status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
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wdinfo("Status :\n");
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wdinfo(" flags : %08x\n", status->flags);
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wdinfo(" timeout : %d\n", status->timeout);
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wdinfo(" timeleft : %d\n", status->flags);
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return OK;
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}
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/****************************************************************************
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* Name: stm32_settimeout
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*
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* Description:
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* Set a new timeout value (and reset the watchdog timer)
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the
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* "lower-half" driver state structure.
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* timeout - The new timeout value in milliseconds.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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uint32_t timeout)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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uint32_t fwwdg;
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uint32_t reload;
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uint16_t regval;
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int wdgtb;
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DEBUGASSERT(priv);
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wdinfo("Entry: timeout=%d\n", timeout);
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/* Can this timeout be represented? */
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if (timeout < 1 || timeout > WWDG_MAXTIMEOUT)
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{
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wderr("ERROR: Cannot represent timeout=%d > %d\n",
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timeout, WWDG_MAXTIMEOUT);
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return -ERANGE;
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}
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/* Determine prescaler value.
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*
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* Fwwdg = PCLK1/4096/prescaler.
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*
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* Where
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* Fwwwdg is the frequency of the WWDG clock
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* wdgtb is one of {1, 2, 4, or 8}
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*/
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/* Select the smallest prescaler that will result in a reload field value that is
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* less than the maximum.
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*/
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for (wdgtb = 0; ; wdgtb++)
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{
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/* WDGTB = 0 -> Divider = 1 = 1 << 0
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* WDGTB = 1 -> Divider = 2 = 1 << 1
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* WDGTB = 2 -> Divider = 4 = 1 << 2
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* WDGTB = 3 -> Divider = 8 = 1 << 3
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*/
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/* Get the WWDG counter frequency in Hz. */
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fwwdg = (STM32_PCLK1_FREQUENCY/4096) >> wdgtb;
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/* The formula to calculate the timeout value is given by:
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*
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* timeout = 1000 * (reload + 1) / Fwwdg, OR
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* reload = timeout * Fwwdg / 1000 - 1
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*
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* Where
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* timeout is the desired timout in milliseconds
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* reload is the contents of T{5:0]
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* Fwwdg is the frequency of the WWDG clock
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*/
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reload = timeout * fwwdg / 1000 - 1;
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/* If this reload valid is less than the maximum or we are not ready
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* at the prescaler value, then break out of the loop to use these
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* settings.
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*/
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||
|
||
#if 0
|
||
wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
|
||
wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg);
|
||
#endif
|
||
if (reload <= WWDG_CR_T_MAX || wdgtb == 3)
|
||
{
|
||
/* Note that we explicitly break out of the loop rather than using
|
||
* the 'for' loop termination logic because we do not want the
|
||
* value of wdgtb to be incremented.
|
||
*/
|
||
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* Make sure that the final reload value is within range */
|
||
|
||
if (reload > WWDG_CR_T_MAX)
|
||
{
|
||
reload = WWDG_CR_T_MAX;
|
||
}
|
||
|
||
/* Calculate and save the actual timeout value in milliseconds:
|
||
*
|
||
* timeout = 1000 * (reload + 1) / Fwwdg
|
||
*/
|
||
|
||
priv->timeout = 1000 * (reload + 1) / fwwdg;
|
||
|
||
/* Remember the selected values */
|
||
|
||
priv->fwwdg = fwwdg;
|
||
priv->reload = reload;
|
||
|
||
wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
|
||
wdgtb, fwwdg, reload, priv->timeout);
|
||
|
||
/* Set WDGTB[1:0] bits according to calculated value */
|
||
|
||
regval = stm32_getreg(STM32_WWDG_CFR);
|
||
regval &= ~WWDG_CFR_WDGTB_MASK;
|
||
regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT;
|
||
stm32_putreg(regval, STM32_WWDG_CFR);
|
||
|
||
/* Reset the 7-bit window value to the maximum value.. essentially disabling
|
||
* the lower limit of the watchdog reset time.
|
||
*/
|
||
|
||
stm32_setwindow(priv, 0x7f);
|
||
return OK;
|
||
}
|
||
|
||
/****************************************************************************
|
||
* Name: stm32_capture
|
||
*
|
||
* Description:
|
||
* Don't reset on watchdog timer timeout; instead, call this user provider
|
||
* timeout handler. NOTE: Providing handler==NULL will restore the reset
|
||
* behavior.
|
||
*
|
||
* Input Parameters:
|
||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||
* driver state structure.
|
||
* newhandler - The new watchdog expiration function pointer. If this
|
||
* function pointer is NULL, then the reset-on-expiration
|
||
* behavior is restored,
|
||
*
|
||
* Returned Values:
|
||
* The previous watchdog expiration function pointer or NULL is there was
|
||
* no previous function pointer, i.e., if the previous behavior was
|
||
* reset-on-expiration (NULL is also returned if an error occurs).
|
||
*
|
||
****************************************************************************/
|
||
|
||
static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
|
||
xcpt_t handler)
|
||
{
|
||
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
|
||
irqstate_t flags;
|
||
xcpt_t oldhandler;
|
||
uint16_t regval;
|
||
|
||
DEBUGASSERT(priv);
|
||
wdinfo("Entry: handler=%p\n", handler);
|
||
|
||
/* Get the old handler return value */
|
||
|
||
flags = enter_critical_section();
|
||
oldhandler = priv->handler;
|
||
|
||
/* Save the new handler */
|
||
|
||
priv->handler = handler;
|
||
|
||
/* Are we attaching or detaching the handler? */
|
||
|
||
regval = stm32_getreg(STM32_WWDG_CFR);
|
||
if (handler)
|
||
{
|
||
/* Attaching... Enable the EWI interrupt */
|
||
|
||
regval |= WWDG_CFR_EWI;
|
||
stm32_putreg(regval, STM32_WWDG_CFR);
|
||
|
||
up_enable_irq(STM32_IRQ_WWDG);
|
||
}
|
||
else
|
||
{
|
||
/* Detaching... Disable the EWI interrupt */
|
||
|
||
regval &= ~WWDG_CFR_EWI;
|
||
stm32_putreg(regval, STM32_WWDG_CFR);
|
||
|
||
up_disable_irq(STM32_IRQ_WWDG);
|
||
}
|
||
|
||
leave_critical_section(flags);
|
||
return oldhandler;
|
||
}
|
||
|
||
/****************************************************************************
|
||
* Name: stm32_ioctl
|
||
*
|
||
* Description:
|
||
* Any ioctl commands that are not recognized by the "upper-half" driver
|
||
* are forwarded to the lower half driver through this method.
|
||
*
|
||
* Input Parameters:
|
||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||
* driver state structure.
|
||
* cmd - The ioctl command value
|
||
* arg - The optional argument that accompanies the 'cmd'. The
|
||
* interpretation of this argument depends on the particular
|
||
* command.
|
||
*
|
||
* Returned Values:
|
||
* Zero on success; a negated errno value on failure.
|
||
*
|
||
****************************************************************************/
|
||
|
||
static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
|
||
unsigned long arg)
|
||
{
|
||
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
|
||
int ret = -ENOTTY;
|
||
|
||
DEBUGASSERT(priv);
|
||
wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
|
||
|
||
/* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
|
||
* are received within this time, a reset event will be generated.
|
||
* Argument: A 32-bit time value in milliseconds.
|
||
*/
|
||
|
||
if (cmd == WDIOC_MINTIME)
|
||
{
|
||
uint32_t mintime = (uint32_t)arg;
|
||
|
||
/* The minimum time should be strictly less than the total delay
|
||
* which, in turn, will be less than or equal to WWDG_CR_T_MAX
|
||
*/
|
||
|
||
ret = -EINVAL;
|
||
if (mintime < priv->timeout)
|
||
{
|
||
uint32_t window = (priv->timeout - mintime) * priv->fwwdg / 1000 - 1;
|
||
DEBUGASSERT(window < priv->reload);
|
||
stm32_setwindow(priv, window | WWDG_CR_T_RESET);
|
||
ret = OK;
|
||
}
|
||
}
|
||
|
||
return ret;
|
||
}
|
||
|
||
/****************************************************************************
|
||
* Public Functions
|
||
****************************************************************************/
|
||
|
||
/****************************************************************************
|
||
* Name: stm32_wwdginitialize
|
||
*
|
||
* Description:
|
||
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
|
||
* registers as 'devpath. The initial state of the watchdog time is
|
||
* disabled.
|
||
*
|
||
* Input Parameters:
|
||
* devpath - The full path to the watchdog. This should be of the form
|
||
* /dev/watchdog0
|
||
*
|
||
* Returned Values:
|
||
* None
|
||
*
|
||
****************************************************************************/
|
||
|
||
void stm32_wwdginitialize(FAR const char *devpath)
|
||
{
|
||
FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
|
||
|
||
wdinfo("Entry: devpath=%s\n", devpath);
|
||
|
||
/* NOTE we assume that clocking to the IWDG has already been provided by
|
||
* the RCC initialization logic.
|
||
*/
|
||
|
||
/* Initialize the driver state structure. Here we assume: (1) the state
|
||
* structure lies in .bss and was zeroed at reset time. (2) This function
|
||
* is only called once so it is never necessary to re-zero the structure.
|
||
*/
|
||
|
||
priv->ops = &g_wdgops;
|
||
|
||
/* Attach our EWI interrupt handler (But don't enable it yet) */
|
||
|
||
(void)irq_attach(STM32_IRQ_WWDG, stm32_interrupt);
|
||
|
||
/* Select an arbitrary initial timeout value. But don't start the watchdog
|
||
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
|
||
* device option bits, the watchdog is automatically enabled at power-on.
|
||
*/
|
||
|
||
stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
|
||
CONFIG_STM32_WWDG_DEFTIMOUT);
|
||
|
||
/* Register the watchdog driver as /dev/watchdog0 */
|
||
|
||
(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
|
||
|
||
/* When the microcontroller enters debug mode (Cortex<65>-M4F core halted),
|
||
* the WWDG counter either continues to work normally or stops, depending
|
||
* on DBG_WWDG_STOP configuration bit in DBG module.
|
||
*/
|
||
|
||
#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
|
||
defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
|
||
defined(CONFIG_STM32_JTAG_SW_ENABLE)
|
||
{
|
||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||
defined(CONFIG_STM32_STM32F40XX)
|
||
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
|
||
cr |= DBGMCU_APB1_WWDGSTOP;
|
||
putreg32(cr, STM32_DBGMCU_APB1_FZ);
|
||
#else /* if defined(CONFIG_STM32_STM32F10XX) */
|
||
uint32_t cr = getreg32(STM32_DBGMCU_CR);
|
||
cr |= DBGMCU_CR_WWDGSTOP;
|
||
putreg32(cr, STM32_DBGMCU_CR);
|
||
#endif
|
||
}
|
||
#endif
|
||
}
|
||
|
||
#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */
|