251 lines
8.7 KiB
C
251 lines
8.7 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_dumpgpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/* Output debug info even if debug output is not selected. */
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#undef CONFIG_DEBUG_INFO
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#define CONFIG_DEBUG_INFO 1
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#include <sys/types.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#ifdef CONFIG_DEBUG_FEATURES
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Port letters for prettier debug output */
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static const char g_portchar[STM32_NGPIO_PORTS] =
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{
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#if STM32_NGPIO_PORTS > 11
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# error "Additional support required for this number of GPIOs"
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#elif STM32_NGPIO_PORTS > 10
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
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#elif STM32_NGPIO_PORTS > 9
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
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#elif STM32_NGPIO_PORTS > 8
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
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#elif STM32_NGPIO_PORTS > 7
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'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
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#elif STM32_NGPIO_PORTS > 6
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'A', 'B', 'C', 'D', 'E', 'F', 'G'
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#elif STM32_NGPIO_PORTS > 5
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'A', 'B', 'C', 'D', 'E', 'F'
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#elif STM32_NGPIO_PORTS > 4
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'A', 'B', 'C', 'D', 'E'
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#elif STM32_NGPIO_PORTS > 3
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'A', 'B', 'C', 'D'
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#elif STM32_NGPIO_PORTS > 2
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'A', 'B', 'C'
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#elif STM32_NGPIO_PORTS > 1
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'A', 'B'
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#elif STM32_NGPIO_PORTS > 0
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'A'
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#else
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# error "Bad number of GPIOs"
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#endif
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};
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: stm32_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the provided base address
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*
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****************************************************************************/
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int stm32_dumpgpio(uint32_t pinset, const char *msg)
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{
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irqstate_t flags;
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uint32_t base;
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unsigned int port;
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/* Get the base address associated with the GPIO port */
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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base = g_gpiobase[port];
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/* The following requires exclusive access to the GPIO registers */
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flags = enter_critical_section();
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#if defined(CONFIG_STM32_STM32F10XX)
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
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{
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_info(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_CRH_OFFSET),
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getreg32(base + STM32_GPIO_CRL_OFFSET),
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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_info(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
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getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
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getreg32(STM32_AFIO_EXTICR1),
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getreg32(STM32_AFIO_EXTICR2),
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getreg32(STM32_AFIO_EXTICR3),
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getreg32(STM32_AFIO_EXTICR4));
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}
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else
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{
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_info(" GPIO%c not enabled: APB2ENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_APB2ENR));
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}
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#elif defined(CONFIG_STM32_STM32L15XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
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{
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_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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_info(" AFRH: %08x AFRL: %08x\n",
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getreg32(base + STM32_GPIO_AFRH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET));
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}
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else
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{
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_info(" GPIO%c not enabled: AHBENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_AHBENR));
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}
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#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
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defined(CONFIG_STM32_STM32F33XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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/* GPIOs are always enabled */
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_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
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getreg32(base + STM32_GPIO_AFRH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET),
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getreg32(base + STM32_GPIO_BRR_OFFSET));
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
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{
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_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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_info(" AFRH: %08x AFRL: %08x\n",
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getreg32(base + STM32_GPIO_AFRH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET));
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}
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else
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{
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_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
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}
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#elif defined(CONFIG_STM32_STM32G4XXX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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_info("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
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{
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_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
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getreg32(base + STM32_GPIO_AFRH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET),
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getreg32(base + STM32_GPIO_BRR_OFFSET));
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}
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else
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{
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_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_AHB2ENR));
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}
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#else
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# error "Unsupported STM32 chip"
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#endif
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leave_critical_section(flags);
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return OK;
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}
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#endif /* CONFIG_DEBUG_FEATURES */
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