533 lines
13 KiB
C
533 lines
13 KiB
C
/****************************************************************************
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* drivers/virtio/virtio-gpu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __DRIVERS_VIRTIO_VIRTIO_GPU_H
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#define __DRIVERS_VIRTIO_VIRTIO_GPU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/compiler.h>
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#include <nuttx/config.h>
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#include <sys/types.h>
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#ifdef CONFIG_DRIVERS_VIRTIO_GPU
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* Definitions from viogpu.h in OpenBSD src */
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#define VIRTIO_GPU_F_VIRGL (1u << 0)
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#define VIRTIO_GPU_F_EDID (1u << 1)
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#define VIRTIO_GPU_F_RESOURCE_UUID (1u << 2)
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#define VIRTIO_GPU_F_RESOURCE_BLOB (1u << 3)
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enum virtio_gpu_ctrl_type
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{
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VIRTIO_GPU_UNDEFINED = 0,
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/* 2d commands */
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VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
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VIRTIO_GPU_CMD_RESOURCE_UNREF,
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VIRTIO_GPU_CMD_SET_SCANOUT,
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VIRTIO_GPU_CMD_RESOURCE_FLUSH,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
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VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
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VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
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VIRTIO_GPU_CMD_GET_CAPSET_INFO,
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VIRTIO_GPU_CMD_GET_CAPSET,
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VIRTIO_GPU_CMD_GET_EDID,
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VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
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VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
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/* 3d commands */
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VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
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VIRTIO_GPU_CMD_CTX_DESTROY,
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VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
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VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
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VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
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VIRTIO_GPU_CMD_SUBMIT_3D,
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VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
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VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
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/* Cursor commands */
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VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
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VIRTIO_GPU_CMD_MOVE_CURSOR,
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/* Success responses */
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VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
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VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET,
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VIRTIO_GPU_RESP_OK_EDID,
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VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
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VIRTIO_GPU_RESP_OK_MAP_INFO,
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/* Error responses */
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VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
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VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
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VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
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};
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enum virtio_gpu_shm_id
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{
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VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
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VIRTIO_GPU_SHM_ID_HOST_VISIBLE
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};
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
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begin_packed_struct struct virtio_gpu_ctrl_hdr
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{
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uint32_t type;
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uint32_t flags;
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uint64_t fence_id;
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uint32_t ctx_id;
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uint8_t ring_idx;
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uint8_t padding[3];
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} end_packed_struct;
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/* Data passed in the cursor vq */
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begin_packed_struct struct virtio_gpu_cursor_pos
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{
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uint32_t scanout_id;
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uint32_t x;
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uint32_t y;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
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begin_packed_struct struct virtio_gpu_update_cursor
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_cursor_pos pos; /* Update & move */
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uint32_t resource_id; /* Update only */
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uint32_t hot_x; /* Update only */
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uint32_t hot_y; /* Update only */
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uint32_t padding;
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} end_packed_struct;
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/* Data passed in the control vq, 2d related */
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begin_packed_struct struct virtio_gpu_rect
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{
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uint32_t x;
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uint32_t y;
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uint32_t width;
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uint32_t height;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
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begin_packed_struct struct virtio_gpu_resource_unref
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
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begin_packed_struct struct virtio_gpu_resource_create_2d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t format;
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uint32_t width;
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uint32_t height;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_SET_SCANOUT */
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begin_packed_struct struct virtio_gpu_set_scanout
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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uint32_t scanout_id;
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uint32_t resource_id;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
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begin_packed_struct struct virtio_gpu_resource_flush
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
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begin_packed_struct struct virtio_gpu_transfer_to_host_2d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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uint64_t offset;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
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begin_packed_struct struct virtio_gpu_mem_entry
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{
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uint64_t addr;
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uint32_t length;
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uint32_t padding;
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} end_packed_struct;
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begin_packed_struct struct virtio_gpu_resource_attach_backing
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t nr_entries;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
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begin_packed_struct struct virtio_gpu_resource_detach_backing
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
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#define VIRTIO_GPU_MAX_SCANOUTS 16
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begin_packed_struct struct virtio_gpu_resp_display_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_display_one
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{
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struct virtio_gpu_rect r;
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uint32_t enabled;
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uint32_t flags;
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}
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pmodes[VIRTIO_GPU_MAX_SCANOUTS];
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} end_packed_struct;
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/* Data passed in the control vq, 3d related */
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begin_packed_struct struct virtio_gpu_box
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{
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uint32_t x;
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uint32_t y;
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uint32_t z;
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uint32_t w;
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uint32_t h;
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uint32_t d;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
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begin_packed_struct struct virtio_gpu_transfer_host_3d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_box box;
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uint64_t offset;
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uint32_t resource_id;
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uint32_t level;
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uint32_t stride;
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uint32_t layer_stride;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
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#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
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begin_packed_struct struct virtio_gpu_resource_create_3d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t target;
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uint32_t format;
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uint32_t bind;
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uint32_t width;
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uint32_t height;
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uint32_t depth;
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uint32_t array_size;
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uint32_t last_level;
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uint32_t nr_samples;
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uint32_t flags;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_CTX_CREATE */
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begin_packed_struct struct virtio_gpu_ctx_create
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t nlen;
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uint32_t padding;
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char debug_name[64];
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_CTX_DESTROY */
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begin_packed_struct struct virtio_gpu_ctx_destroy
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{
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struct virtio_gpu_ctrl_hdr hdr;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
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begin_packed_struct struct virtio_gpu_ctx_resource
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_SUBMIT_3D */
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begin_packed_struct struct virtio_gpu_cmd_submit
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t size;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
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#define VIRTIO_GPU_CAPSET_VIRGL 1
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#define VIRTIO_GPU_CAPSET_VIRGL2 2
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begin_packed_struct struct virtio_gpu_get_capset_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t capset_index;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
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begin_packed_struct struct virtio_gpu_resp_capset_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t capset_id;
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uint32_t capset_max_version;
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uint32_t capset_max_size;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_GET_CAPSET */
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begin_packed_struct struct virtio_gpu_get_capset
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t capset_id;
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uint32_t capset_version;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_CAPSET */
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begin_packed_struct struct virtio_gpu_resp_capset
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint8_t capset_data[];
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_GET_EDID */
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begin_packed_struct struct virtio_gpu_cmd_get_edid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t scanout;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_EDID */
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begin_packed_struct struct virtio_gpu_resp_edid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t size;
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uint32_t padding;
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uint8_t edid[1024];
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} end_packed_struct;
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#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
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begin_packed_struct struct virtio_gpu_config
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{
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uint32_t events_read;
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uint32_t events_clear;
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uint32_t num_scanouts;
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uint32_t num_capsets;
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} end_packed_struct;
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/* simple formats for fbcon/X use */
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enum virtio_gpu_formats
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{
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VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
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VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
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VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
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VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
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VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
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VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
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VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
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VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
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};
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/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
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begin_packed_struct struct virtio_gpu_resource_assign_uuid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
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begin_packed_struct struct virtio_gpu_resp_resource_uuid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint8_t uuid[16];
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
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#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
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#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
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#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
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#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
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#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
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#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
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begin_packed_struct struct virtio_gpu_resource_create_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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/* Zero is invalid blob mem */
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uint32_t blob_mem;
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uint32_t blob_flags;
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uint32_t nr_entries;
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uint64_t blob_id;
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uint64_t size;
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/* sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow */
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
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begin_packed_struct struct virtio_gpu_set_scanout_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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uint32_t scanout_id;
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uint32_t resource_id;
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uint32_t width;
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uint32_t height;
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uint32_t format;
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uint32_t padding;
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uint32_t strides[4];
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uint32_t offsets[4];
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
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begin_packed_struct struct virtio_gpu_resource_map_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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uint64_t offset;
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} end_packed_struct;
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/* VIRTIO_GPU_RESP_OK_MAP_INFO */
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#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
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#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
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#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
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#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
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#define VIRTIO_GPU_MAP_CACHE_WC 0x03
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begin_packed_struct struct virtio_gpu_resp_map_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t map_info;
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uint32_t padding;
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} end_packed_struct;
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/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
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begin_packed_struct struct virtio_gpu_resource_unmap_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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} end_packed_struct;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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|
****************************************************************************/
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|
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int virtio_register_gpu_driver(void);
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|
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int virtio_gpu_fb_register(int display);
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#undef EXTERN
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#ifdef __cplusplus
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|
}
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#endif
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#endif /* CONFIG_DRIVERS_VIRTIO_GPU */
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#endif /* __DRIVERS_VIRTIO_VIRTIO_GPU_H */
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