2192d83200
Add support for XSAVE/XRSTOR to handle x86_64 procesor extended states. Support for these instructions is required to support AVX instruction set Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
809 lines
20 KiB
C
809 lines
20 KiB
C
/****************************************************************************
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* arch/x86_64/include/intel64/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_X86_64_INCLUDE_INTEL64_IRQ_H
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#define __ARCH_X86_64_INCLUDE_INTEL64_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# include <time.h>
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#endif
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#include <arch/arch.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ISR and IRQ numbers */
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#define ISR0 0 /* Division by zero exception */
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#define ISR1 1 /* Debug exception */
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#define ISR2 2 /* Non maskable interrupt */
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#define ISR3 3 /* Breakpoint exception */
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#define ISR4 4 /* 'Into detected overflow' */
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#define ISR5 5 /* Out of bounds exception */
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#define ISR6 6 /* Invalid opcode exception */
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#define ISR7 7 /* No coprocessor exception */
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#define ISR8 8 /* Double fault (pushes an error code) */
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#define ISR9 9 /* Coprocessor segment overrun */
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#define ISR10 10 /* Bad TSS (pushes an error code) */
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#define ISR11 11 /* Segment not present (pushes an error code) */
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#define ISR12 12 /* Stack fault (pushes an error code) */
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#define ISR13 13 /* General protection fault (pushes an error code) */
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#define ISR14 14 /* Page fault (pushes an error code) */
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#define ISR15 15 /* Unknown interrupt exception */
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#define ISR16 16 /* Coprocessor fault */
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#define ISR17 17 /* Alignment check exception */
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#define ISR18 18 /* Machine check exception */
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#define ISR19 19 /* SIMD Float-Point Exception*/
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#define ISR20 20 /* Virtualization Exception */
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#define ISR21 21 /* Reserved */
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#define ISR22 22 /* Reserved */
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#define ISR23 23 /* Reserved */
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#define ISR24 24 /* Reserved */
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#define ISR25 25 /* Reserved */
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#define ISR26 26 /* Reserved */
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#define ISR27 27 /* Reserved */
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#define ISR28 28 /* Reserved */
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#define ISR29 29 /* Reserved */
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#define ISR30 30 /* Security Exception */
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#define ISR31 31 /* Reserved */
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#define IRQ0 32 /* System timer (cannot be changed) */
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#define IRQ1 33 /* Keyboard controller (cannot be changed) */
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#define IRQ2 34 /* Cascaded signals from IRQs 8~15 */
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#define IRQ3 35 /* Serial port controller for COM2/4 */
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#define IRQ4 36 /* serial port controller for COM1/3 */
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#define IRQ5 37 /* LPT port 2 or sound card */
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#define IRQ6 38 /* Floppy disk controller */
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#define IRQ7 39 /* LPT port 1 or sound card */
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#define IRQ8 40 /* Real time clock (RTC) */
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#define IRQ9 41 /* Open interrupt/available or SCSI host adapter */
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#define IRQ10 42 /* Open interrupt/available or SCSI or NIC */
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#define IRQ11 43 /* Open interrupt/available or SCSI or NIC */
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#define IRQ12 44 /* Mouse on PS/2 connector */
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#define IRQ13 45 /* Math coprocessor */
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#define IRQ14 46 /* Primary ATA channel */
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#define IRQ15 47 /* Secondary ATA channel */
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#define IRQ16 48
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#define IRQ17 49
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#define IRQ18 50
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#define IRQ19 51
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#define IRQ20 52
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#define IRQ21 53
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#define IRQ22 54
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#define IRQ23 55
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#define IRQ24 56
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#define IRQ25 57
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#define IRQ26 58
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#define IRQ27 59
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#define IRQ28 60
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#define IRQ29 61
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#define IRQ30 62
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#define IRQ31 63
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#define IRQ32 64
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#define IRQ33 65
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#define IRQ34 66
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#define IRQ35 67
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#define IRQ36 68
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#define IRQ37 69
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#define IRQ38 70
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#define IRQ39 71
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#define IRQ40 72
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#define IRQ41 73
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#define IRQ42 74
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#define IRQ43 75
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#define IRQ44 76
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#define IRQ45 77
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#define IRQ46 78
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#define IRQ47 79
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#define IRQ48 80
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#define IRQ49 81
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#define IRQ50 82
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#define IRQ51 83
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#define IRQ52 84
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#define IRQ53 85
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#define IRQ54 86
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#define IRQ55 87
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#define IRQ56 88
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#define IRQ57 89
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#define IRQ58 90
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#define IRQ59 91
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#define IRQ60 92
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#define IRQ61 93
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#define IRQ62 94
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#define IRQ63 95
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#define IRQ64 96
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#define IRQ65 97
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#define IRQ66 98
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#define IRQ67 99
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#define IRQ68 100
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#define IRQ69 101
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#define IRQ70 102
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#define IRQ71 103
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#define IRQ72 104
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#define IRQ73 105
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#define IRQ74 106
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#define IRQ75 107
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#define IRQ76 108
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#define IRQ77 109
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#define IRQ78 110
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#define IRQ79 111
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#define IRQ80 112
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#define IRQ81 113
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#define IRQ82 114
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#define IRQ83 115
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#define IRQ84 116
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#define IRQ85 117
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#define IRQ86 118
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#define IRQ87 119
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#define IRQ88 120
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#define IRQ89 121
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#define IRQ90 122
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#define IRQ91 123
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#define IRQ92 124
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#define IRQ93 125
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#define IRQ94 126
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#define IRQ95 127
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#define IRQ96 128
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#define IRQ97 129
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#define IRQ98 130
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#define IRQ99 131
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#define IRQ100 132
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#define IRQ101 133
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#define IRQ102 134
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#define IRQ103 135
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#define IRQ104 136
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#define IRQ105 137
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#define IRQ106 138
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#define IRQ107 139
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#define IRQ108 140
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#define IRQ109 141
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#define IRQ110 142
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#define IRQ111 143
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#define IRQ112 144
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#define IRQ113 145
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#define IRQ114 146
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#define IRQ115 147
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#define IRQ116 148
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#define IRQ117 149
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#define IRQ118 150
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#define IRQ119 151
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#define IRQ120 152
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#define IRQ121 153
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#define IRQ122 154
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#define IRQ123 155
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#define IRQ124 156
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#define IRQ125 157
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#define IRQ126 158
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#define IRQ127 159
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#define IRQ128 160
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#define IRQ129 161
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#define IRQ130 162
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#define IRQ131 163
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#define IRQ132 164
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#define IRQ133 165
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#define IRQ134 166
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#define IRQ135 167
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#define IRQ136 168
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#define IRQ137 169
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#define IRQ138 170
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#define IRQ139 171
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#define IRQ140 172
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#define IRQ141 173
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#define IRQ142 174
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#define IRQ143 175
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#define IRQ144 176
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#define IRQ145 177
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#define IRQ146 178
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#define IRQ147 179
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#define IRQ148 180
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#define IRQ149 181
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#define IRQ150 182
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#define IRQ151 183
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#define IRQ152 184
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#define IRQ153 185
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#define IRQ154 186
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#define IRQ155 187
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#define IRQ156 188
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#define IRQ157 189
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#define IRQ158 190
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#define IRQ159 191
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#define IRQ160 192
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#define IRQ161 193
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#define IRQ162 194
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#define IRQ163 195
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#define IRQ164 196
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#define IRQ165 197
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#define IRQ166 198
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#define IRQ167 199
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#define IRQ168 200
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#define IRQ169 201
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#define IRQ170 202
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#define IRQ171 203
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#define IRQ172 204
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#define IRQ173 205
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#define IRQ174 206
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#define IRQ175 207
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#define IRQ176 208
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#define IRQ177 209
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#define IRQ178 210
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#define IRQ179 211
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#define IRQ180 212
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#define IRQ181 213
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#define IRQ182 214
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#define IRQ183 215
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#define IRQ184 216
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#define IRQ185 217
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#define IRQ186 218
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#define IRQ187 219
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#define IRQ188 220
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#define IRQ189 221
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#define IRQ190 222
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#define IRQ191 223
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#define IRQ192 224
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#define IRQ193 225
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#define IRQ194 226
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#define IRQ195 227
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#define IRQ196 228
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#define IRQ197 229
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#define IRQ198 230
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#define IRQ199 231
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#define IRQ200 232
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#define IRQ201 233
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#define IRQ202 234
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#define IRQ203 235
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#define IRQ204 236
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#define IRQ205 237
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#define IRQ206 238
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#define IRQ207 239
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#define IRQ208 240
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#define IRQ209 241
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#define IRQ210 242
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#define IRQ211 243
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#define IRQ212 244
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#define IRQ213 245
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#define IRQ214 246
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#define IRQ215 247
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#define IRQ216 248
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#define IRQ217 249
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#define IRQ218 250
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#define IRQ219 251
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#define IRQ220 252
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#define IRQ221 253
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#define IRQ222 254
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#define IRQ223 255
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#define IRQ224 256
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#define IRQ225 257
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#define IRQ226 258
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#define IRQ227 259
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#define IRQ228 260
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#define IRQ229 261
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#define IRQ230 262
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#define IRQ231 263
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#define IRQ232 264
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#define IRQ233 265
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#define IRQ234 266
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#define IRQ235 267
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#define IRQ236 268
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#define IRQ237 269
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#define IRQ238 270
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#define IRQ239 271
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#define IRQ240 272
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#define IRQ241 273
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#define IRQ242 274
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#define IRQ243 275
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#define IRQ244 276
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#define IRQ245 277
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#define IRQ246 278
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#define IRQ247 279
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#define IRQ248 280
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#define IRQ249 281
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#define IRQ250 282
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#define IRQ251 283
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#define IRQ252 284
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#define IRQ253 285
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#define IRQ254 286
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#define IRQ255 287
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#define NR_IRQS 288
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#define MAX_NR_IRQS 255
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#define IRQ_ERROR 51 /* APIC Error */
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#define IRQ_SPURIOUS 0xff /* Spurious Interrupts */
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/* Use legacy routing for HPET */
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#define HPET0_IRQ IRQ2
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#define HPET1_IRQ IRQ8
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/* Use IRQ15 for SMP */
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#define SMP_IPI_IRQ IRQ15
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/* Common register save structure created by up_saveusercontext() and by
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* ISR/IRQ interrupt processing.
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*/
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#ifndef CONFIG_ARCH_X86_64_HAVE_XSAVE
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/* Only legacy area if XSAVE not supported */
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# define XCPTCONTEXT_XMM_AREA_SIZE 512
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#else
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/* XSAVE state depneds on enabled features */
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# ifdef CONFIG_ARCH_X86_64_AVX
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# define XSTATE_AVX_STATE X86_XSAVE_AVX
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# define XSTATE_AVX_SIZE XSAVE_AVX_SIZE
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# else
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# define XSTATE_AVX_STATE 0
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# define XSTATE_AVX_SIZE 0
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# endif
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# ifdef CONFIG_ARCH_X86_64_AVX512
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# define XSTATE_AVX512_STATE (X86_XSAVE_AVX512_OPMASK | \
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X86_XSAVE_AVX512_HI256 | \
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X86_XSAVE_AVX512_HI16)
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# define XSTATE_AVX512_SIZE (XSAVE_MXP_BNDREGS_SIZE + \
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XSAVE_MXP_BNDCSR_SIZE + \
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XSAVE_AVX512OPMASK_SIZE + \
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XSAVE_AVX512HI256_SIZE + \
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XSAVE_AVX512HI16_SIZE)
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# else
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# define XSTATE_AVX512_STATE 0
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# define XSTATE_AVX512_SIZE 0
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# endif
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/* State component bitmap */
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# define XSAVE_STATE_COMPONENTS (X86_XSAVE_X87 | \
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X86_XSAVE_SSE | \
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XSTATE_AVX_STATE | \
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XSTATE_AVX512_STATE)
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/* Area for XSAVE - standard area format */
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# define XCPTCONTEXT_XMM_AREA_SIZE (XSAVE_LEGACY_SIZE + \
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XSAVE_HEADER_SIZE + \
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XSTATE_AVX_SIZE + \
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XSTATE_AVX512_SIZE)
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#endif
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/* Align registers to 64-bytes */
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#ifdef CONFIG_ARCH_X86_64_AVX512
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# define XMMAREA_REG_ALIGN (13)
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#else
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# define XMMAREA_REG_ALIGN (7)
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#endif
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/* Register offset in XMMAREA */
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#define XMMAREA_OFFSET (XCPTCONTEXT_XMM_AREA_SIZE / 8)
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#define XMMAREA_REG_OFFSET (XMMAREA_REG_ALIGN + XMMAREA_OFFSET)
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/* Data segments */
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#define REG_FS (0 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_GS (1 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_ES (2 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_DS (3 + XMMAREA_REG_OFFSET) /* Data segment selector */
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/* Remaining regs */
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#define REG_RAX (4 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RBX (5 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RBP (6 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R10 (7 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R11 (8 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R12 (9 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R13 (10 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R14 (11 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R15 (12 + XMMAREA_REG_OFFSET) /* " " "" " " */
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/* ABI calling convention */
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#define REG_R9 (13 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_R8 (14 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RCX (15 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RDX (16 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RSI (17 + XMMAREA_REG_OFFSET) /* " " "" " " */
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#define REG_RDI (18 + XMMAREA_REG_OFFSET) /* " " "" " " */
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/* IRQ saved */
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#define REG_ERRCODE (19 + XMMAREA_REG_OFFSET) /* Error code */
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#define REG_RIP (20 + XMMAREA_REG_OFFSET) /* Pushed by process on interrupt processing */
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#define REG_CS (21 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_RFLAGS (22 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_RSP (23 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define REG_SS (24 + XMMAREA_REG_OFFSET) /* " " "" " " "" " " " " */
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#define XMMAREA_REGS (25)
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/* NOTE 2: This is not really state data. Rather, this is just a convenient
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* way to pass parameters from the interrupt handler to C code.
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*/
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#define XCPTCONTEXT_REGS (XMMAREA_REGS + XMMAREA_REG_ALIGN + \
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XCPTCONTEXT_XMM_AREA_SIZE / 8)
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#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
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/* Always align XCPTCONTEXT to 64-bytes to support XSAVE */
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#define XCPTCONTEXT_ALIGN (64)
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#define XCP_ALIGN_MASK (XCPTCONTEXT_ALIGN - 1)
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#define XCP_ALIGN_DOWN(a) ((a) & ~XCP_ALIGN_MASK)
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#define XCP_ALIGN_UP(a) (((a) + XCP_ALIGN_MASK) & ~XCP_ALIGN_MASK)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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enum ioapic_trigger_mode
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{
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TRIGGER_RISING_EDGE = 0,
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TRIGGER_FALLING_EDGE = (1 << 13),
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TRIGGER_LEVEL_ACTIVE_HIGH = 1 << 15,
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TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
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};
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/* This struct defines the way the registers are stored */
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of instruction pointer and EFLAGS used during
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* signal processing.
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*/
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uint64_t saved_rip;
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uint64_t saved_rflags;
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uint64_t saved_rsp;
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/* Register save area - allocated from stack in up_initial_state() */
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uint64_t *regs;
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};
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Inline functions
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
static inline void setgdt(void *gdt, int size)
|
|
{
|
|
struct gdt_ptr_s gdt_ptr;
|
|
gdt_ptr.limit = size;
|
|
gdt_ptr.base = (uintptr_t)gdt;
|
|
|
|
asm volatile ("lgdt %0"::"m"(gdt_ptr):"memory");
|
|
}
|
|
|
|
static inline void setidt(void *idt, int size)
|
|
{
|
|
struct idt_ptr_s idt_ptr;
|
|
idt_ptr.limit = size;
|
|
idt_ptr.base = (uintptr_t)idt;
|
|
|
|
asm volatile ("lidt %0"::"m"(idt_ptr):"memory");
|
|
}
|
|
|
|
static inline uint64_t rdtsc(void)
|
|
{
|
|
uint32_t lo;
|
|
uint32_t hi;
|
|
|
|
asm volatile("rdtscp" : "=a" (lo), "=d" (hi)::"memory");
|
|
return (uint64_t)lo | (((uint64_t)hi) << 32);
|
|
}
|
|
|
|
static inline uint64_t _rdtsc(void)
|
|
{
|
|
uint32_t lo;
|
|
uint32_t hi;
|
|
|
|
asm volatile("rdtsc" : "=a" (lo), "=d" (hi)::"memory");
|
|
return (uint64_t)lo | (((uint64_t)hi) << 32);
|
|
}
|
|
|
|
static inline void set_pcid(uint64_t pcid)
|
|
{
|
|
if (pcid < 4095)
|
|
{
|
|
asm volatile("mov %%cr3, %%rbx; andq $-4096, %%rbx; or %0, "
|
|
"%%rbx; mov %%rbx, %%cr3;"
|
|
::"g"(pcid):"memory", "rbx", "rax");
|
|
}
|
|
}
|
|
|
|
static inline unsigned long read_msr(unsigned int msr)
|
|
{
|
|
uint32_t low;
|
|
uint32_t high;
|
|
|
|
asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
|
|
return low | ((unsigned long)high << 32);
|
|
}
|
|
|
|
static inline void write_msr(unsigned int msr, unsigned long val)
|
|
{
|
|
asm volatile("wrmsr"
|
|
: /* no output */
|
|
: "c" (msr), "a" (val), "d" (val >> 32)
|
|
: "memory");
|
|
}
|
|
|
|
static inline uint64_t read_fsbase(void)
|
|
{
|
|
uint64_t val;
|
|
asm volatile("rdfsbase %0"
|
|
: "=r" (val)
|
|
: /* no output */
|
|
: "memory");
|
|
|
|
return val;
|
|
}
|
|
|
|
static inline void write_fsbase(unsigned long val)
|
|
{
|
|
asm volatile("wrfsbase %0"
|
|
: /* no output */
|
|
: "r" (val)
|
|
: "memory");
|
|
}
|
|
|
|
static inline uint64_t read_gsbase(void)
|
|
{
|
|
uint64_t val;
|
|
asm volatile("rdgsbase %0"
|
|
: "=r" (val)
|
|
: /* no output */
|
|
: "memory");
|
|
|
|
return val;
|
|
}
|
|
|
|
static inline void write_gsbase(unsigned long val)
|
|
{
|
|
asm volatile("wrgsbase %0"
|
|
: /* no output */
|
|
: "r" (val)
|
|
: "memory");
|
|
}
|
|
|
|
/* Return stack pointer */
|
|
|
|
static inline uint64_t up_getsp(void)
|
|
{
|
|
uint64_t regval;
|
|
|
|
asm volatile(
|
|
"\tmovq %%rsp, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
/* Get segment registers */
|
|
|
|
static inline uint32_t up_getds(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%ds, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getcs(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%cs, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getss(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%ss, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getes(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%es, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getfs(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%fs, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
static inline uint32_t up_getgs(void)
|
|
{
|
|
uint32_t regval;
|
|
|
|
asm volatile(
|
|
"\tmov %%gs, %0\n"
|
|
: "=rm" (regval)
|
|
:
|
|
: "memory");
|
|
return regval;
|
|
}
|
|
|
|
/* Name: up_irq_save, up_irq_restore, and friends.
|
|
*
|
|
* NOTE: This function should never be called from application code and,
|
|
* as a general rule unless you really know what you are doing, this
|
|
* function should not be called directly from operation system code either:
|
|
* Typically, the wrapper functions, enter_critical_section() and
|
|
* leave_critical section(), are probably what you really want.
|
|
*/
|
|
|
|
/* Get the current FLAGS register contents */
|
|
|
|
static inline irqstate_t irqflags()
|
|
{
|
|
irqstate_t flags;
|
|
|
|
asm volatile(
|
|
"\tpushfq\n"
|
|
"\tpopq %0\n"
|
|
: "=rm" (flags)
|
|
:
|
|
: "memory");
|
|
return flags;
|
|
}
|
|
|
|
/* Get a sample of the FLAGS register, determine if interrupts are disabled.
|
|
* If the X86_FLAGS_IF is cleared by cli, then interrupts are disabled. If
|
|
* if the X86_FLAGS_IF is set by sti, then interrupts are enable.
|
|
*/
|
|
|
|
static inline bool up_irq_disabled(irqstate_t flags)
|
|
{
|
|
return ((flags & X86_64_RFLAGS_IF) == 0);
|
|
}
|
|
|
|
static inline bool up_irq_enabled(irqstate_t flags)
|
|
{
|
|
return ((flags & X86_64_RFLAGS_IF) != 0);
|
|
}
|
|
|
|
/* Disable interrupts unconditionally */
|
|
|
|
static inline void up_irq_disable(void)
|
|
{
|
|
asm volatile("cli": : :"memory");
|
|
}
|
|
|
|
/* Enable interrupts unconditionally */
|
|
|
|
static inline void up_irq_enable(void)
|
|
{
|
|
asm volatile("sti": : :"memory");
|
|
}
|
|
|
|
/* Disable interrupts, but return previous interrupt state */
|
|
|
|
static inline irqstate_t up_irq_save(void)
|
|
{
|
|
irqstate_t flags = irqflags();
|
|
up_irq_disable();
|
|
return flags;
|
|
}
|
|
|
|
/* Conditionally disable interrupts */
|
|
|
|
static inline void up_irq_restore(irqstate_t flags)
|
|
{
|
|
if (up_irq_enabled(flags))
|
|
{
|
|
up_irq_enable();
|
|
}
|
|
}
|
|
|
|
static inline unsigned int up_apic_cpu_id(void)
|
|
{
|
|
return read_msr(MSR_X2APIC_ID);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
void up_ioapic_pin_set_vector(unsigned int pin,
|
|
enum ioapic_trigger_mode trigger_mode,
|
|
unsigned int vector);
|
|
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __ARCH_X86_INCLUDE_I486_IRQ_H */
|
|
|