137 lines
5.7 KiB
C
137 lines
5.7 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/arm.h
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* Non-CP15 Registers
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
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* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
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* ARM DDI 0406C.b (ID072512)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_CPSR_H
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#define __ARCH_ARM_SRC_ARMV7_A_CPSR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ARMv7-A ******************************************************************/
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/* PSR bits */
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#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */
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#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT)
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# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */
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# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */
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# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */
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# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */
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# define PSR_MODE_MON (22 << PSR_MODE_SHIFT) /* Monitor mode */
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# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */
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# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hyp mode */
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# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */
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# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */
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#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */
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#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */
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#define PSR_MASK_MASK (7 << PSR_GE_SHIFT)
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# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */
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# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */
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# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */
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#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */
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#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */
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#define PSR_GE_MASK (15 << PSR_GE_SHIFT)
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/* Bits 20-23: Reserved. RAZ/SBZP */
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#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */
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#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */
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#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT)
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#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */
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#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */
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#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */
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#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */
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#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: arm_data_initialize
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*
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* Description:
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* Clear all of .bss to zero; set .data to the correct initial values
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arm_data_initialize(void);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_CPSR_H */
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