544 lines
12 KiB
C
544 lines
12 KiB
C
/****************************************************************************
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* boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "rx65n_macrodriver.h"
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#include "rx65n_port.h"
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#include "arch/board/board.h"
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#include "arch/board/rx65n_gpio.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: led_port_create
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*
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* Description:
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* LED Port Initialization for RX65N GRROSE Board
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****************************************************************************/
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#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
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void led_port_create(void)
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{
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/* LED Port initialization of RX65N GRROSE */
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LED_PORTINIT(0);
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}
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/****************************************************************************
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* Name: sci_port_create
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*
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* Description:
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* SCI Port Initialization for RX65N GRROSE Board
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****************************************************************************/
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void sci_port_create(void)
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{
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/* SCI Port initialization for RX65N-GRROSE */
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/* SCI0(UART) direction */
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PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
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/* SCI2(UART) direction */
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PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
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/* SCI5(UART) direction */
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PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
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/* SCI6(UART) direction */
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PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
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/* SCI8(RS485) direction */
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PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
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}
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/****************************************************************************
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* Name: r_ether_pheriperal_enable
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*
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* Description:
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* Ethernet Pheriperal enabling
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****************************************************************************/
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#ifdef CONFIG_RX65N_EMAC0
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void r_ether_pheriperal_enable(void)
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{
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/* Set ET0_MDC(PA4_ET_MDC) pin */
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MPC.PA4PFS.BYTE = 0x11u;
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PORTA.PMR.BIT.B4 = 1u;
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/* Set ET0_MDIO(PA3_ET_MDIO) pin */
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MPC.PA3PFS.BYTE = 0x11u;
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PORTA.PMR.BIT.B3 = 1u;
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/* Set REF50CK0 (PB2_ET_CLK) pin */
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MPC.PB2PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B2 = 1u;
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/* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
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MPC.PB7PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B7 = 1u;
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/* Set RMII0_RXD0(PB1_ET_RXD0) pin */
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MPC.PB1PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B1 = 1u;
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/* Set RMII0_RXD1(PB0_ET_RXD1) pin */
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MPC.PB0PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.BT0 = 1u;
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/* Set RMII0_RX_ER(PB3_ET_RXER) pin */
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MPC.PB3PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B3 = 1u;
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/* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
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MPC.PB5PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B5 = 1u;
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/* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
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MPC.PB6PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B6 = 1u;
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/* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
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MPC.PB4PFS.BYTE = 0x12u;
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PORTB.PMR.BIT.B4 = 1u;
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/* Set RXD2 pin */
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MPC.P52PFS.BYTE = 0x0au;
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PORT5.PMR.BIT.B2 = 1u;
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/* Set TXD2 pin */
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PORT5.PODR.BYTE |= 0x01u;
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MPC.P50PFS.BYTE = 0x0au;
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PORT5.PDR.BYTE |= 0x01u;
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/* Set ET0_LINKSTA(PA5_ET_LINK) pin */
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MPC.PA5PFS.BYTE = 0x11u;
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PORTA.PMR.BIT.B5 = 1u;
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/* Set ETHER reset(PA6_ET_RST) pin */
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MPC.PA6PFS.BYTE = 0x12u;
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PORTA.PMR.BIT.B6 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: r_usbdev_port_enable
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*
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* Description:
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* USB Device enabling
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****************************************************************************/
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#ifdef CONFIG_USBDEV
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void r_usbdev_port_enable(void)
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{
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/* Set USB0_VBUS pin */
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MPC.P16PFS.BYTE = 0x11;
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PORT1.PMR.BIT.B6 = 1;
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}
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#endif
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/****************************************************************************
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* Name: r_usb_port_enable
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*
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* Description:
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* USB Enabling for RX65N RSK2MB
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****************************************************************************/
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#if defined(CONFIG_USBHOST)
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void r_usb_port_enable(void)
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{
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/* Set VBUS pin for USB */
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MPC.P16PFS.BYTE = 0x11u;
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/* PORT1.PMR.BYTE |= 0x40; */
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PORT1.PMR.BIT.B6 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci0_init_port
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*
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* Description:
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* SCI0 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI0
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inline void sci0_init_port(void)
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{
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/* Set RXD0 pin (P21) */
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MPC.P21PFS.BYTE = 0x0au;
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PORT2.PMR.BIT.B1 = 1u;
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/* Set TXD0 pin (P20) */
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PORT2.PODR.BIT.BT0 = 1u;
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MPC.P20PFS.BYTE = 0x0au;
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PORT2.PDR.BIT.BT0 = 1u;
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PORT2.PMR.BIT.BT0 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci1_init_port
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*
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* Description:
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* SCI1 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI1
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inline void sci1_init_port(void)
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{
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/* Set RXD1 pin (P30) */
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MPC.P30PFS.BYTE = 0x0au;
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PORT3.PMR.BIT.BT0 = 1u;
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/* Set TXD1 pin (P26) */
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PORT2.PODR.BIT.B6 = 1u;
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MPC.P26PFS.BYTE = 0x0au;
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PORT2.PDR.BIT.B6 = 1u;
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PORT2.PMR.BIT.B6 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci2_init_port
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*
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* Description:
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* SCI2 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI2
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inline void sci2_init_port(void)
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{
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/* Set RXD2 pin (P12) */
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MPC.P12PFS.BYTE = 0x0au;
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PORT1.PMR.BIT.B2 = 1u;
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/* Set TXD2 pin (P13) */
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PORT1.PODR.BIT.B3 = 1u;
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MPC.P13PFS.BYTE = 0x0au;
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PORT1.PDR.BIT.B3 = 1u;
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PORT1.PMR.BIT.B3 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci3_init_port
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*
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* Description:
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* SCI3 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI3
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inline void sci3_init_port(void)
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{
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/* Set RXD3 pin (PXX)
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* MPC.PXXPFS.BYTE = 0x0au;
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* PORTX.PMR.BIT.BX = 1u;
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* Set TXD3 pin (PXX)
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* PORTX.PODR.BIT.BX = 1u;
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* MPC.PXXPFS.BYTE = 0x0au;
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* PORTX.PDR.BIT.BX = 1u;
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* PORTX.PMR.BIT.BX = 1u;
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*/
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/* Set RXD2 pin (P25) */
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MPC.P25PFS.BYTE = 0x0au;
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PORT2.PMR.BIT.B5 = 1u;
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/* Set TXD2 pin (P23) */
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PORT2.PODR.BIT.B3 = 1u;
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MPC.P23PFS.BYTE = 0x0au;
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PORT2.PDR.BIT.B3 = 1u;
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PORT2.PMR.BIT.B3 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci5_init_port
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*
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* Description:
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* SCI5 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI5
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inline void sci5_init_port(void)
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{
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/* Set RXD3 pin (PC2) */
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MPC.PC2PFS.BYTE = 0x0au;
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PORTC.PMR.BIT.B2 = 1u;
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/* Set TXD3 pin (PC3) */
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PORTC.PODR.BIT.B3 = 1u;
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MPC.PC3PFS.BYTE = 0x0au;
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PORTC.PDR.BIT.B3 = 1u;
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PORTC.PMR.BIT.B3 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci6_init_port
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*
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* Description:
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* SCI6 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI6
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inline void sci6_init_port(void)
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{
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/* Set RXD6 pin (P33) */
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MPC.P33PFS.BYTE = 0x0au;
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PORT3.PMR.BIT.B3 = 1u;
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/* Set TXD6 pin (P32) */
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PORT3.PODR.BIT.B2 = 1u;
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MPC.P32PFS.BYTE = 0x0au;
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PORT3.PDR.BIT.B2 = 1u;
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PORT3.PMR.BIT.B2 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: sci8_init_port
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*
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* Description:
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* SCI8 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_SCI8
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inline void sci8_init_port(void)
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{
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/* Set RXD8 pin (PC6) */
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MPC.PC6PFS.BYTE = 0x0au;
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PORTC.PMR.BIT.B6 = 1u;
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/* Set TXD8 pin (PC7) */
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PORTC.PODR.BIT.B7 = 1u;
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MPC.PC7PFS.BYTE = 0x0au;
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PORTC.PDR.BIT.B7 = 1u;
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PORTC.PMR.BIT.B7 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: rspi_pinconfig
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*
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* Description: RSPI pinconfiguration for channel
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*
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* Input Parameters:
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* Port number (for hardware that has multiple SPI interfaces)
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*
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* Description:
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*RSPI pin(SCK,MOSI and MISO) configuration
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****************************************************************************/
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#ifdef CONFIG_RX65N_RSPI
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void rspi_pinconfig(int bus)
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{
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/* Set RSPI signal ports to peripheral mode */
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switch (bus)
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{
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case RX65N_RSPI_CHANNEL0:
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#ifdef CONFIG_RX65N_RSPI0
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/* Configure RSPCKA */
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MPC.PC5PFS.BYTE = 0x0d;
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PORTC.PMR.BIT.B5 = 1;
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/* Configure MOSIA */
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MPC.PC6PFS.BYTE = 0x0d; /* This config will block SCI8 function */
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PORTC.PMR.BIT.B6 = 1;
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/* Configure MISOA */
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MPC.PC7PFS.BYTE = 0x0d; /* This config will block SCI8 function */
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PORTC.PMR.BIT.B7 = 1;
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/* Configure SSLA0 */
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MPC.PC4PFS.BYTE = 0x0d;
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PORTC.PMR.BIT.B4 = 1;
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#endif
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break;
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case RX65N_RSPI_CHANNEL1:
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#ifdef CONFIG_RX65N_RSPI1
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/* Configure RSPCKB */
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MPC.PE5PFS.BYTE = 0x0d;
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PORTE.PMR.BIT.B5 = 1;
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/* Configure MOSIB */
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MPC.PE6PFS.BYTE = 0x0d;
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PORTE.PMR.BIT.B6 = 1;
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/* Configure MISOB */
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MPC.PE7PFS.BYTE = 0x0d;
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PORTE.PMR.BIT.B7 = 1;
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/* Configure SSLB0 */
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MPC.PE4PFS.BYTE = 0x0d;
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PORTE.PMR.BIT.B4 = 1;
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#endif
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break;
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case RX65N_RSPI_CHANNEL2:
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#ifdef CONFIG_RX65N_RSPI2
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/* Configure RSPCKC */
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MPC.PD3PFS.BYTE = 0x0d;
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PORTD.PMR.BIT.B3 = 1;
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/* Configure MOSIC */
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MPC.PD1PFS.BYTE = 0x0d;
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PORTD.PMR.BIT.B1 = 1;
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/* Configure MISOC */
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MPC.PD2PFS.BYTE = 0x0d;
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PORTD.PMR.BIT.B2 = 1;
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/* Configure SSLC0 */
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MPC.PD4PFS.BYTE = 0x0d;
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PORTD.PMR.BIT.B4 = 1;
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#endif
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break;
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default:
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break;
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}
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}
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#endif
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/****************************************************************************
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* Name: riic0_init_port
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*
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* Description:
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* RIIC0 Initialization RX65N GRROSE
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****************************************************************************/
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#ifdef CONFIG_RX65N_RIIC0
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inline void riic0_init_port(void)
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{
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/* Set SCL0 pin (P12) */
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MPC.P12PFS.BYTE = 0x0fu;
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PORT1.PMR.BIT.B2 = 1u;
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/* Set SDA0 pin (P13) */
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MPC.P13PFS.BYTE = 0x0fu;
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PORT1.PMR.BIT.B3 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: riic1_init_port
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*
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* Description:
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* RIIC1 Initialization RX65N RSK2MB
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****************************************************************************/
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#ifdef CONFIG_RX65N_RIIC1
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inline void riic1_init_port(void)
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{
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/* Set SCL0 pin (P21) */
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MPC.P21PFS.BYTE = 0x0fu;
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PORT2.PMR.BIT.B1 = 1u;
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/* Set SDA0 pin (P20) */
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MPC.P20PFS.BYTE = 0x0fu;
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PORT2.PMR.BIT.BT0 = 1u;
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}
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#endif
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/****************************************************************************
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* Name: riic2_init_port
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*
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* Description:
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* RIIC2 Initialization RX65N RSK2MB
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****************************************************************************/
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#ifdef CONFIG_RX65N_RIIC2
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inline void riic2_init_port(void)
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{
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/* Set SCL0 pin (P16) */
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MPC.P16PFS.BYTE = 0x0fu;
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PORT1.PMR.BIT.B6 = 1u;
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/* Set SDA0 pin (P17) */
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MPC.P17PFS.BYTE = 0x0fu;
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PORT1.PMR.BIT.B7 = 1u;
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}
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#endif
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#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ |