nuttx/libs/libc/machine/sim
Ville Juven 996625ec58 riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:

label:
	auipc      a0, %pcrel_hi(symbol)    // R_RISCV_PCREL_HI20
	load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S

With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).

However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.

The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2023-12-12 17:32:36 -08:00
..
arch_elf64.c riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly 2023-12-12 17:32:36 -08:00
arch_elf.c riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly 2023-12-12 17:32:36 -08:00
arch_setjmp_arm64.S
arch_setjmp_arm.S
arch_setjmp_x86_64.S fix sim register & tcb info typo 2023-07-23 21:59:35 -07:00
arch_setjmp_x86.asm
arch_setjmp_x86.S
CMakeLists.txt build: add initial cmake build system 2023-07-08 13:50:48 +08:00
Kconfig
Make.defs