e5dfd805e6
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
100 lines
4.8 KiB
Plaintext
100 lines
4.8 KiB
Plaintext
/****************************************************************************
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* configs/lpc4088-devkit/scripts/memory.ld
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 96KB of total SRAM: 64KB of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8KB at addresses
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* 0x20000000 bank0 first and 8KB at 0x20002000 at bank0 second. And 16KB
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* at 0x20004000 on bank1.
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*
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* For MPU support, the kernel-mode NuttX section is assumed to be 256KB of
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* FLASH and 4KB of SRAM. That, of course, can be optimized as needed (See
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* also configs/lpc4088-devkit/scripts/kernel-space.ld); 256KB is probably much
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* more than is needed by the RTOS! That size is selected only because it
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* is available due to alignment issues for the user space FLASH memory.
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*
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* Alignment of the user space FLASH partition is a critical factor: The
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* user space FLASH partition will be spanned with a single region of size
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* 2**n bytes. The alignment of the user-space region must be the same. As
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* a consequence, as the user-space increases in size, the alignmment
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* requirement also increases.
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*
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* This alignment requirement means that the largest user space FLASH region
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* you can have will be 256KB at it would have to be positioned at
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* 0x00400000. If you change this address, don't forget to change the
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* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
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* the check in kernel/userspace.c.
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*
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* For the same reasons, the maximum size of the SRAM mapping is limited to
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* 4KB. Both of these alignment limitations could be reduced by using
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* multiple regions to map the FLASH/SDRAM range or perhaps with some
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* clever use of subregions.
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*
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* A detailed memory map for the 64KB CPU SRAM region is as follows:
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*
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* 0x10000 0000: Kernel .data region. Typical size: 0.1KB
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* ------- ---- Kernel .bss region. Typical size: 1.8KB
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* 0x10000 0800: Kernel IDLE thread stack (approximate). Size is
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* determined by CONFIG_IDLETHREAD_STACKSIZE and
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* adjustments for alignment. Typical is 1KB.
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* ------- ---- Padded to 4KB
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* 0x10000 1000: User .data region. Size is variable.
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* ------- ---- User .bss region Size is variable.
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* ------- ---- Beginning of kernel heap. Size determined by
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* CONFIG_MM_KERNEL_HEAPSIZE.
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* 0x10000 8000: Beginning of user heap. Can vary with other settings.
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* 0x10001 0000: End+1 of CPU RAM
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*/
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MEMORY
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{
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/* 256Kb FLASH */
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kflash (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* More than needed */
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uflash (rx) : ORIGIN = 0x00040000, LENGTH = 256K
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/* 64Kb of SRAM in the CPU block */
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ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 4K /* May include waste */
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usram (rwx) : ORIGIN = 0x10001000, LENGTH = 4K
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xsram (rwx) : ORIGIN = 0x10002000, LENGTH = 24K /* All used as heap */
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/* Other peripheral memory (free, nothing is linked here) */
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ahbram8_b0a(rwx) : ORIGIN = 0x20000000, LENGTH = 8K
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ahbram8_b0b(rwx) : ORIGIN = 0x20002000, LENGTH = 8K
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ahbram16(rwx) : ORIGIN = 0x20004000, LENGTH = 16K
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}
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