7b7b4e0377
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4733 42af7a65-404d-4744-a932-0658087f49c3
153 lines
4.8 KiB
C
153 lines
4.8 KiB
C
/****************************************************************************
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* arch/arm/src/calypso/calypso_uwire.c
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* Driver for Calypso uWire Master Controller
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*
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* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
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*
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* This source code is derivated from Osmocom-BB project and was
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* relicensed as BSD with permission from original authors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include <stdio.h>
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#include <debug.h>
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#include "up_arch.h"
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#define BASE_ADDR_UWIRE 0xfffe4000
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#define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n))
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enum uwire_regs {
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REG_DATA = 0x00,
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REG_CSR = 0x02,
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REG_SR1 = 0x04,
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REG_SR2 = 0x06,
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REG_SR3 = 0x08,
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};
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#define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
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#define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
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#define UWIRE_CSR_IDX(n) (((n) & 3) << 10)
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#define UWIRE_CSR_CS_CMD (1 << 12)
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#define UWIRE_CSR_START (1 << 13)
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#define UWIRE_CSR_CSRB (1 << 14)
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#define UWIRE_CSR_RDRB (1 << 15)
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#define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */
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#define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */
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#define UWIRE_CSn_CS_LVL (1 << 2)
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#define UWIRE_CSn_FRQ_DIV2 (0 << 3)
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#define UWIRE_CSn_FRQ_DIV4 (1 << 3)
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#define UWIRE_CSn_FRQ_DIV8 (2 << 3)
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#define UWIRE_CSn_CKH
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#define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0)
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#define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1)
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#define UWIRE_SR3_CLK_EN (1 << 0)
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#define UWIRE_SR3_CLK_DIV2 (0 << 1)
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#define UWIRE_SR3_CLK_DIV4 (1 << 1)
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#define UWIRE_SR3_CLK_DIV7 (2 << 1)
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#define UWIRE_SR3_CLK_DIV10 (3 << 1)
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static inline void _uwire_wait(int mask, int val)
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{
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while ((getreg16(UWIRE_REG(REG_CSR)) & mask) != val);
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}
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void uwire_init(void)
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{
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putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
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/* FIXME only init CS0 for now */
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putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
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UWIRE_REG(UWIRE_CSn_REG(0)));
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putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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}
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int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
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{
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uint16_t tmp = 0;
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if (bitlen <= 0 || bitlen > 16)
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return -1;
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if (cs < 0 || cs > 4)
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return -1;
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/* FIXME uwire_init always selects CS0 for now */
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dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
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/* select the chip */
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putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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if (dout) {
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if (bitlen <= 8)
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tmp = *(uint8_t *)dout;
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else if (bitlen <= 16)
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tmp = *(uint16_t *)dout;
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tmp <<= 16 - bitlen; /* align to MSB */
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putreg16(tmp, UWIRE_REG(REG_DATA));
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dbg(", data_out=0x%04hx", tmp);
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}
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tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
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(din ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
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UWIRE_CSR_START;
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putreg16(tmp, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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if (din) {
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_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
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tmp = getreg16(UWIRE_REG(REG_DATA));
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dbg(", data_in=0x%08x", tmp);
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if (bitlen <= 8)
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*(uint8_t *)din = tmp & 0xff;
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else if (bitlen <= 16)
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*(uint16_t *)din = tmp & 0xffff;
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}
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/* unselect the chip */
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putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
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_uwire_wait(UWIRE_CSR_CSRB, 0);
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dbg(")\n");
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return 0;
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}
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