169 lines
11 KiB
C
169 lines
11 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_SYSCFG_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_SYSCFG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
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#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
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#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
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# define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
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# define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
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# define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
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# define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
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#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG CCMSRAM control and status register */
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#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
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#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG CCMSRAM write protection register */
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#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG CCMSRAM key register */
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/* Register Addresses *******************************************************/
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#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET)
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#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
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#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p))
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# define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET)
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# define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET)
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# define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET)
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# define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET)
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#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET)
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#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET)
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#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET)
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#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* Memory remap register (MEMRMP) */
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#define SYSCFG_MEMRMP_MEM_MODE_SHIFT (0)
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#define SYSCFG_MEMRMP_MEM_MODE_MASK (0x7 << SYSCFG_MEMRMP_MEM_MODE_SHIFT)
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# define SYSCFG_MEMRMP_MEM_MODE_FLASH (0x0 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* Main Flash memory mapped at 0x00000000 */
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# define SYSCFG_MEMRMP_MEM_MODE_SYSTEM (0x1 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* System Flash memory mapped at 0x00000000 */
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# define SYSCFG_MEMRMP_MEM_MODE_FSMC (0x2 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* FSMC memory */
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# define SYSCFG_MEMRMP_MEM_MODE_SRAM1 (0x3 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* SRAM1 mapped at 0x00000000 */
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# define SYSCFG_MEMRMP_MEM_MODE_QSPI (0x4 << SYSCFG_MEMRMP_MEM_MODE_SHIFT) /* QUADSPI memory mapped at 0x00000000 */
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#define SYSCFG_MEMRMP_FB_MODE_MASK (1 << 8) /* User Flash Bank mode selection */
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/* Configuration register 1 (CFGR1) */
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#define SYSCFG_CFGR1_BOOSTEN_MASK (1 << 8) /* I/O analog switch voltage booster enable */
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#define SYSCFG_CFGR1_ANASWVDD_MASK (1 << 9) /* GPIO analog switch control voltage selection */
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#define SYSCFG_CFGR1_I2C_PB6_FMP_MASK (1 << 16) /* I2C PB6 fast mode plus */
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#define SYSCFG_CFGR1_I2C_PB7_FMP_MASK (1 << 17) /* I2C PB7 fast mode plus */
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#define SYSCFG_CFGR1_I2C_PB8_FMP_MASK (1 << 18) /* I2C PB8 fast mode plus */
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#define SYSCFG_CFGR1_I2C_PB9_FMP_MASK (1 << 19) /* I2C PB9 fast mode plus */
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#define SYSCFG_CFGR1_I2C1_FMP_MASK (1 << 20) /* I2C1 fast mode plus */
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#define SYSCFG_CFGR1_I2C2_FMP_MASK (1 << 21) /* I2C2 fast mode plus */
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#define SYSCFG_CFGR1_I2C3_FMP_MASK (1 << 22) /* I2C3 fast mode plus */
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#define SYSCFG_CFGR1_I2C4_FMP_MASK (1 << 23) /* I2C4 fast mode plus */
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#define SYSCFG_CFGR1_FPUIE_INVALIDOP (1 << 26) /* Invalid operation interrupt enable */
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#define SYSCFG_CFGR1_FPUIE_DIVZERO (1 << 27) /* Divide by zero interrupt enable */
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#define SYSCFG_CFGR1_FPUIE_UNDERFLOW (1 << 28) /* Underflow interrupt enable */
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#define SYSCFG_CFGR1_FPUIE_OVERFLOW (1 << 29) /* Overflow interrupt enable */
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#define SYSCFG_CFGR1_FPUIE_DENORMAL (1 << 30) /* Input denormal interrupt enable */
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#define SYSCFG_CFGR1_FPUIE_INEXACT (1 << 31) /* Inexact interrupt enable */
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/* External interrupt (EXTI) configuration registers 1-4 (EXTICR1..4) */
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#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
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#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
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#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
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#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
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#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
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#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
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#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
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#define SYSCFG_EXTICR_PORT_MASK (15)
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#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
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#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
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#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
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#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
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#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
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#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
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#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
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#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
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#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
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#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
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#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
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#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
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#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
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#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
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#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
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#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
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#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
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#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
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#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
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#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
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#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
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#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
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#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
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#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
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#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
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#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
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#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
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#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
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#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
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#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
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#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
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#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
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#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
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#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
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/* CCM SRAM control and status register (SCSR) */
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#define SYSCFG_SCSR_CCMER (1 << 0) /* CCMSRAM Erase Request */
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#define SYSCFG_SCSR_CCMBSY (1 << 1) /* CCMSRAM Erase In Progress */
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/* Configuration register 2 (CFGR2) */
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#define SYSCFG_CFGR2_CLL (1 << 0) /* Cortex M4 lockup (HARDFAULT) output enable bit */
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#define SYSCFG_CFGR2_SPL (1 << 1) /* SRAM1 and CCM SRAM parity lock */
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#define SYSCFG_CFGR2_PVDL (1 << 2) /* PVD lock enable bit */
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#define SYSCFG_CFGR2_ECCL (1 << 3) /* ECC lock */
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#define SYSCFG_CFGR2_SPF (1 << 8) /* SRAM1 and CCM STAM parity error flag */
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/* CCM SRAM write protection register (SWPR) */
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#define SYSCFG_SWPR_PWP(n) (1 << (n)) /* CCMSRAM Write protection for page n=0..31 */
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/* CCM SRAM key register (SKR) */
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#define SYSCFG_SKR_KEY_SHIFT (0) /* CCMSRAM write protection key for software erase */
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#define SYSCFG_SKR_KEY_MASK (0xff << SYSCFG_SKR_KEY_SHIFT)
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# define SYSCFG_SKR_KEY(n) (((n) << SYSCFG_SKR_KEY_SHIFT) & SYSCFG_SKR_KEY_MASK)
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#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_SYSCFG_H */
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